Theory of Operation
—
DM 5010
generated by
the Timing Logic and
the comparison data
from
the
Charge-Balancing Converter to automatically se
quence through
the complex and varied measurement
functions.
To
initiate
a measurement, the
microprocessor generates
a low
/TRIG via the Address Decode circuitry. This TRIG
pulse is
latched by U1530A and U1530B
and sets the IN
PROGRESS
line high, telling the microprocessor that the
conversion is
in progress and valid data is not available. The
J
input of U1425A
is set high via U1435C
and, at
the begin
ning of the next measurement interval (falling edge of T17),
the
M/Z
(measure-zero) level is set high. This signal is trans
mitted to
the Charge-Balancing Converter via the opto
isolators
and initiates its measurement sequence. The Q
output of U1425A
sets the
J input of
U1230A high via
U1530C and, on the next 250 kHz clock (TO), the UP
clock
and
DOWN clock logic,
U1135A and U1135C, is enabled.
The up/down counter now accumulates clock
pulses as
described
in
the
Charge-Balancing Converter description
until
the Timing Logic generates
an EOC (end of count)
pulse
to
U1435A,
signalling that the proper number of
mea
surement intervals
have been completed. This
applies a high
to the
J
input of the
override flip-flop U1330A and the next
clock
pulse (TO)
sets its Q output low. This low is applied to
U1425B and keeps any
subsequent trigger
from passing
through U1435C that might re-initiate the measurement se
quence
before it is completed.
The measure-zero flip-flop is reset on the next clock (the
falling edge of
T17
coincides with rising
T1). The low input to
U1530C
from U1330A keeps the UP counter and DOWN
counter
logic enabled during the override period by keeping
U1230A
’s
J input held high. This enables the data counter
to
keep counting while the Charge-Balancing Converters
in
tegrator
makes
its final charge back to the zero-reference
voltage as explained
in the Charge-Balancing Converter de
scription. Integrated circuits
U1430C
and U1435B reset the
override
flip-flop
when
integrating down (pin 9 of U1330B
high)
and
the zero-reference
voltage is crossed (COMP
goes low).
The next clock pulse after the override flip-flop is
reset
disables
the UP clock and DOWN clock logic by clocking
U1230A
’s Q output low.
This clocks
chop flip-flop U1230B
and
the 250 kHz clock is
enabled through U1435D. The
low
Q
output of the
chop flip-flop holds U1330B
in its set state,
and the cathode of opto-isolator U1710's transmitter LED is
held low. This results in the 250 kHz chopping of the I
U/D
line,
keeping the Charge-Balancing Converters integrator
output
very close to the zero-reference voltage as explained
in that description.
At
the end of the
next
T17,
T17 sets U1230B to disable
the
chopping
clock
and allow U1330B to distribute clocks in
its usual manner.
The clock
enable provided by U1230A to U1135A and
U1135C
allows clock pulses
to be
passed to the data
counter whenever
the A/D
converter is in its measurement
or
override modes. During this time,
generation of either an
UP clock or a
DOWN clock is controlled by U1330B.
T17,
applied to
U1330B's K input, always sets
S
high, enabling
UP
clocks to
the data counter on the next clock (TO).
Any
of four gates OR’d
together by U1335A have
the
ability to generate a DOWN clock enable, depending on the
converters operating
mode.
When generating the squarewave
I U/D required
for
Auto-Zero,
T17 initiates a series of UP clocks, starting at TO
as
mentioned
above.
Integrated circuit U1430A detects T8
when operating in the Auto-Zero mode and applies a high to
U1330B
’
s J
input via U1335A. The next clock to U1330B
(T9)
initiates
a series
of 9
DOWN clocks. At T17, the cycle
repeats
itself.
When
in the measurement mode, clock pulses
between
T1
and T16 may be either high or low, as described in the
Charge-Balancing Converter description, but all
must be the
same.
This determination
is made at the end of TO by
U1335B.
When measuring, the
M/Z level at pin 12 is high.
Pin
13 is high during all of TO, the time when the decision
about
T1-T16 must
be made. If the COMP (comparator out
put) level from
the A/D converter is high at the end of TO
(indicating
the integrators output is above the zero-refer
ence voltage), a high is applied to the
J input of U1330B via
U1335B
and U1335A.
The next clock pulse (T1)
sets
U1330
’s Q output
high and T1-T17 are DOWN clocks to
the
Data counter. If the COMP level were low at clock T1, all of
the T1-T16
clocks
would
be UP clocks, since U1330B did
not
change.
In
either case, T17 is always a DOWN clock as deter
mined by U1430D. During
T16 when in the measurement
mode,
a high is applied to pin 11
of U1330B via U1430D and
U1335A.
The
next clock
(T17) clocks a high to U1330B’s Q
output and
produces a DOWN clock whether T1-T16 are
DOWN
clocks or not.
During
the
override
period,
clocks must be enabled to the
Data
counter,
but only until the integrators output charges
beyond
the zero-reference voltage, going
negative (COMP
goes
high to low). Integrated circuit U1430B detects
when
this
occurs
and, along with U1430C, U1435B, and U1330A,
completely disables all
clocks to the data counter
while the
remainder of the
override period chops the I
U/D line.
ADD
JAN
1982
4-17
Summary of Contents for DM 5010
Page 14: ...DM 5010 2994 00 DM 5010 Programmable Digital Multimeter xii ADD JUL 1986...
Page 27: ...Operating Instructions DM 5010 2994 03 Fig 2 3 DM 5010 front panel controls and connectors 2 3...
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Page 272: ...DM 5010 2994 37 Fig 10 2 Location of DM 5010 adjustments and test points...
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