Theory of Operation—DM
5010
INTEGRATOR
OUTPUT
A.
WITHOUT
RIPPLE
AT
ZERO
VOLTS.
B.
WITH
NOISE CAUSED
BY
MEASUREMENT
LEADS
(CLOCK
GREATLY
SLOWED
OOWN).
2994-21
Fig.
4 -13. Influence of power
line frequency on A/D conversion.
When operating in a
60 Hz environment,
U1720 detects
when 231
measurement
intervals have occurred. This is
equivalent to
16.63 ms or one complete cycle at 60 Hz. At
this
time, U1720 causes
an
EOC to
be generated at the
output of
U1635A,
stopping the A/D conversion.
When operating in a
50 Hz environment, the 50/60 line to
U1720 should
be set low. This disables
U1720 and U1525
counts up
to 278
before the EOC is generated by U1625
and U1635A. This equates to 20.02 ms or
one complete
cycle
at
50 Hz. As can
be seen, in all cases the A/D conver
sion
takes place over
a complete
number of power-line cy
cles, minimizing
conversion errors
caused by noise.
DATA
<6>
As described
earlier, the result of a charge-balancing A/D
conversion is a sequence of pulses. The number of pulses
generated
during
the
conversion
directly represents the con
ditions
at the converters input. The
Data stage counts these
pulses
and later
transfers the accumulated results to the
microprocessor
data bus as required by the processor.
The counter
circuitry consists of four 4-bit up-down
counters cascaded together along with a discrete-gate flip
flop to form
a 17-bit up-down counter.
The counter is
reset
at
the
beginning of a measurement cycle and then counts
either up or
down, depending on the polarity of the Integra
tors output with respect to the Comparators zero-reference
voltage. At the
end of the measurement period, the number
of
clocks
accumulated
(Tzw(ow
.-Tat)ow) by the 17-bit counter is
representative of the input conditions to the A/D converter.
When the conversion is complete
and the results
are
stored
in the counter, the Control Logic signals that conver
sion
data is available to the microprocessor. This data is
transferred from the counter to the
Data Bus one bit at a
time, starting with the
least significant bit.
At
the time the
processor is told that the data is avail
able, U1235
and U1230
are cleared by the Control Logic
pulsing
the
CLR
line low. This sets
the Q output of U1320
high
to enable data to
be
passed through U1030A. Since
the
Q output of U1320A is
low, the data path through
U1030D is disabled
and
the resulting high at its output en
ables
U1030B.
4-20
ADD
JAN
1982
Summary of Contents for DM 5010
Page 14: ...DM 5010 2994 00 DM 5010 Programmable Digital Multimeter xii ADD JUL 1986...
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