Theory of Operation—
DM 5010
the
RAM block is
enabled by
ERAM low and when the write
enable
WE
is
also low. The write-to-RAM may only occur on
a
Valid
Memory Access (VMA) writing B R/W to the RAM
after
the
Data Bus is known to be valid (B 02) as determined
by U1630A.
CMOS
RAM <8>
The CMOS RAM
stage,
U1220, contains the calibration
constants
for
the DM5010. These constants, along with
various algorithms stored
in the firmware ROM, are used by
the
microprocessor to calculate measurement
results.
These
constants
are
stored, as described below, at the time
of
initial
instrument
adjustment. During normal instrument
operation,
the
CMOS RAM looks like ROM to the
microprocessor.
On power up,
transistor Q1123 is turned on and the
CMOS
RAM
may
be enabled by a low ECMOS from the
Address Decode stage.
During normal instrument operation, jumper P1132 is in
the
NORM position and data may
only be read from the
CMOS
RAM
when
ECMOS is
low; R/W is
always
high. Dur
ing
instrument adjustment, however, new calibration
constants
must
be
written into the CMOS RAM. Jumper
P1132
is
moved to its CAL position and the VW (Valid
Write)
signal enables writing to the CMOS RAM in much the
same
way
as writing to
the
normal
RAM.
To
store calibration
constants, a specified signal is ap
plied
to the DM 5010 input and an A/D conversion is per
formed.
The processor is then told to store this data as a
calibration
constant
when the
user presses the front-panel
ENTER
key. This
routine is repeated until all calibration
constants
have been stored. Jumper P1132 is
then returned
to
its NORM position and, for
all practical purposes, the
CMOS
RAM functions as
a ROM.
When instrument power is turned off, transistor Q1
123 is
turned
off and the CS
(Chip Select) input of U1220 is pulled
high
through R1133 up to the
battery supply voltage. This
tri-states the busses of U1220 to minimize power drain from
the Battery
circuit.
BATTERY <$>
A
Battery
circuit is
employed in the DM 5010 to maintain
the calibration contents of the CMOS RAM when the instru
ment
is not connected to
a line-power source via the power
module.
When not driving the data bus (as when the instru
ment
is
off), the CMOS RAM
requires very little power and a
small
battery will maintain the calibration constants for the
extended
periods
between instrument
use.
In normal operation with power applied, power for U1220
comes
from
the
+8 V supply through R1135 and CR1133.
Diode CR1235 holds the
anode voltage of CR1133 at
+
5.6 V. This results
in +5 V being applied to pin
16 of
U1220,
the
positive
supply input. This +5 V is also applied
to R1131, charging
battery BT1121 when the instrument is
operating.
With power removed, U1220 is disabled,
as de
scribed
earlier,
and the current to maintain the contents of
the
CMOS RAM flows
through R1131 from battery BT1121.
MISCELLANEOUS
BUFFER <9>
This stage buffers three of the one-wide
status bits and
the
serial
conversion data onto the data bus so the proces
sor
may read them
when required.
The EMISC (Enable
Miscellaneous) signal from the Ad
dress
Decode circuitry
turns on buffer U1420B. This
en
ables
the
microprocessor to read the data
on the
four
most-
significant bits of the data bus
and make decisions based
on
these
status
and data bits.
Three
of the four bits buffered onto the bus comprise
status-type information.
These bits affect the way
in which
the
microprocessor performs
its various control functions.
Since the A/D
conversion
process operates in either 50
or
60 Hz environment, the microprocessor
must know which
environment
it is operating in.
The 50/60 Hz jumper, P1
723,
is
set to
match
the line frequency of the power source. This
status bit
may
be read from data bus bit 5 as the processor
requires.
The
microprocessor continually checks the output of the
set/reset
latch,
U1720C, which is buffered onto the data
bus. If the Extrigger jumper, P1721, is in the enable position,
a signal applied to the rear interface EXTRIG
connector pin
may be used to initiate triggering.
In normal front-panel op
eration,
jumper P1721 is in
its disable position and a low is
buffered onto Data
Bus bit 4 when status information is
read. With the Extrigger jumper in its Enable
position, a
low
EXTRIG from the rear interface
connector
pin sets the out
put of U1720C
high and the
microprocessor stops its con
version
process after it performs one more complete con
version.
After
the conversion is complete and the results are
properly
stored or transferred, the processor sets ESW
(Enable
Switch) low via the Address Decode circuitry and
the
output of U1720C is reset low. Normal front-panel oper
ation
resumes until another EXTRIG occurs to initiate an
other triggered conversion.
4-24
ADD
JAN
1982
Summary of Contents for DM 5010
Page 14: ...DM 5010 2994 00 DM 5010 Programmable Digital Multimeter xii ADD JUL 1986...
Page 27: ...Operating Instructions DM 5010 2994 03 Fig 2 3 DM 5010 front panel controls and connectors 2 3...
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Page 251: ...Section 8 DM 5010 OPTIONS No options are available 8 1...
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Page 272: ...DM 5010 2994 37 Fig 10 2 Location of DM 5010 adjustments and test points...
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Page 337: ...63 REV JUN 1986...
Page 338: ...FIG 1 EXPLODED DM 5010...
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