Theory
of
Operation
—DM 5010
2994-11
Fig. 4-3.
Simplified DCV signal conditioner buffer amplifier.
same
voltage as the
input of the
buffer amplifier. Operation
al amplifier U1110 and transistors Q1017 and Q1021 form a
unity gain, noninverting amplifier that tracks the input of the
DCV
Signal Conditioner. Hence, the bases of Q1101 and
Q1
111
follow the input signal (plus and minus 6.2 volts, re
spectively,
as determined by
VR1011
and VR1015). The
emitters of Q1101
and Q1
111 (and thus U1210's supplies)
remain
+5.5 volts and —5.5 volts away from the input volt
age,
respectively. Diodes CR1111 and CR1113 allow the
operational amplifiers
supply pins to follow the buffer ampli
fier
input
under transient conditions where Q1
101
or Q1111
might
become reverse
biased.
As
an
example,
let the input to the buffer amplifier start
at
zero
volts. The input to U1110 at pin 3 and, thus, the
buffered
output
at
pin 2 must also be at zero volts. Zener
diodes VR1001
and VR1013 along with resistor R1011 bias
transistors
Q1001
and Q1015 on, allowing current to flow in
Zener diodes VR1011
and VR1015. This sets the bases of
Q1101
and
Q1111 at +6.2 volts and -6.2 volts, respec
tively. Their emitters, and U1210’s supplies, are at +5.5
volts and —5.5 volts, respectively.
If
the
input to the buffer amplifier
goes to
+15 volts, the
input to the
bootstrap buffer also goes to +15
volts. The
output
at
the
emitters of Q1017
and Q1021 goes positive
until
the inverting
input of
U1110 also r15 volts.
The
bases of
Q1101 and Q1111 go to +21.2 volts and
+
8.8
volts, respectively. The
supply voltages at their
emitters
go to +20.5 volts and +9.5 volts, respectively.
The supply voltages
are plus and
minus 5.5 volts from the
input
voltage of the buffer amplifier, so it is operating
in the
middle of its
range.
CHARGE-BALANCING
CONVERTER
<?>
The
Charge-Balancing
Converter is the analog portion of
the A/D Converter
and, along with the Control Logic, Timing
Logic, opto-isolators, and Data stages, changes the analog-
dc
voltage from the input-conditioning circuits to a digital
representation.
It derives its name from the
fact that, during
one
conversion
cycle, the total current added to and sub
tracted from
the input summing node equals zero. Input
buffer
U1120
and
the
charge-balancing IC U1230, along
with
their associated components, comprise
the Charge-
Balancing
Converter stage.
Figure 4-5 shows a diagram of
the stage
with details of the converter IC added
for clarity.
The Block Diagram
illustrates
the
major functional
interconnections used in this description. The Block Dia
gram
description
explains some of the
general charge-bal
ancing concepts that should
be understood before
proceeding with this description.
The A/D
conversion process is based upon two main
time-dependent
periods
called Auto-Zero
and Measure
ment.
The Auto-Zero period involves setting a zero-refer
ence voltage for
the Charge-Balancing Converter. The
actual
conversion on the selected input is performed during
the Measurement
period.
Both are synchronized
to the
microprocessor
clock
by the Timing Logic.
Figure 4-6 illus
trates
some
of
the critical
timing for each period of the con
version process.
Both
of
the
above conversion phases are based on what
are known as
measurement intervals.
The Timing
Logic di
vides the
microprocessor 1
MHz clock down to a 250 kHz
ADD
JAN
1982
4-7
Summary of Contents for DM 5010
Page 14: ...DM 5010 2994 00 DM 5010 Programmable Digital Multimeter xii ADD JUL 1986...
Page 27: ...Operating Instructions DM 5010 2994 03 Fig 2 3 DM 5010 front panel controls and connectors 2 3...
Page 38: ......
Page 134: ......
Page 208: ......
Page 222: ......
Page 250: ......
Page 251: ...Section 8 DM 5010 OPTIONS No options are available 8 1...
Page 252: ......
Page 270: ......
Page 272: ...DM 5010 2994 37 Fig 10 2 Location of DM 5010 adjustments and test points...
Page 273: ......
Page 274: ......
Page 275: ......
Page 276: ...DM 5010 2994 112 DM 5010 BLOCK DIAGRAM...
Page 281: ......
Page 282: ......
Page 291: ......
Page 293: ......
Page 294: ......
Page 297: ......
Page 298: ......
Page 303: ......
Page 304: ...I...
Page 305: ......
Page 310: ......
Page 311: ......
Page 315: ......
Page 318: ......
Page 321: ......
Page 323: ......
Page 326: ......
Page 332: ...2994 57...
Page 334: ......
Page 335: ......
Page 336: ......
Page 337: ...63 REV JUN 1986...
Page 338: ...FIG 1 EXPLODED DM 5010...
Page 339: ......
Page 340: ......
Page 341: ......
Page 347: ......