Theory of Operation—
DM 5010
Figure
4-8
illustrates the override period for measure
ment
periods ending
both above and below the zero-refer
ence voltage.
As shown in the figure, once the Comparator
detects
that the Integrator has charged below the zero-
referenc voltage,
the
Data counter is disabled (all counting is
complete),
and ¾3
clock cycles later the I
U/D line is
chopped at
a 250 kHz
rate (determined by the Control Log
ic). Chopping the Reference Buffer input between
+Vref and
ground
at this high
rate holds the integrators output close to
the
zero-reference voltage until the
next
TO.
More informa
tion about the charge balancing sequences may be found in
the
Control
Logic description.
MEASUREMENT ENABLE <$>
Field effect
transistor Q1514, along with R1514 and
C1514, holds the
I
M/Z control line low for several hundred
milliseconds during
power-on, thus allowing the Auto-Zero
Buffer
Amplifier storage capacitor,
C1139, to charge to
the
zero-reference voltage. Transistors Q1511
and Q1512 com
prise a level
shifting buffer
that shifts the I
M/Z control line
to
a level
compatible with the isolated
logic levels.
ISOLATED
REGULATORS
<2><3>
The
Isolated Regulators stages
on the RMS and ADC
boards regulate the power
from the Isolated Supply stage to
the
levels required by the Isolated Section of the
instrument.
Integrated
circuits U1601, U1603, U1605, U1417,
U1527,
U1525,
and U1515 are
3-terminal regulation devices with
internal current limiting.
Transistor Q1613, VR1514, and
their
associated
components
form a series-pass regulator
referenced
at
—36.9 volts.
Fig.
4-8. Override and
auto-zero timing for measurement period ending.
4-12
ADD
JAN
1982
Summary of Contents for DM 5010
Page 14: ...DM 5010 2994 00 DM 5010 Programmable Digital Multimeter xii ADD JUL 1986...
Page 27: ...Operating Instructions DM 5010 2994 03 Fig 2 3 DM 5010 front panel controls and connectors 2 3...
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Page 251: ...Section 8 DM 5010 OPTIONS No options are available 8 1...
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