TM 11-6625-2980-14
Paired pulses are obtained by pushing both the
DELAY and UNDLY buttons. An initial pulse now occurs
at external trigger time with the second or paired pulse
delayed by the selected delay time. The CONTROL
ERROR light illuminates if the delay is too short or long
for a valid pulse train. A custom delay position is
provided on the DELAY switch. To determine the value
of the capacitor required, multiply the desired delay time
in seconds by 1 X 10-2. For example, a 50 ms delay
time requires a 500 Pf capacitor (50 ms times 1 X 10-2).
Use either a polarized or non-polarized capacitor with a
rating of at least 6 V. If a polarized capacitor is used,
observe the polarity markings. Remove the input board
and connect the capacitor as shown in Fig. 1-2.
Transition Time Selection
The leading and trailing times of the pulses may be
varied by using the TRANSITION TIME control and the
LEADING and TRAILING variable controls. Select the
desired transition time range with the TRANSITION
TIME control and vary the leading and trailing times
independently with the LEADING and TRAILING
controls.
A custom range position is also provided on the
TRANSITION TIME control. To select the correct
capacitor (in Farads) for this range, multiply the desired
transition time (in seconds) measured from 10% to 90%
points, by 4.4 X 10-'. For example, a desired transition
time of 50 ms requires a capacitor of 220 HF. Connect
the capacitor as shown in Fig. 1-3. Use a capacitor with
at least a 10 V rating and observe polarity requirements.
When the transition times become large compared
with the duration or period times and the pulse does not
reach full amplitude, the CONTROL ERROR light will
flash indicating improper control settings.
Output Levels
The output amplitude and offset are selected by
independent pulse LOW LEVEL and HIGH LEVEL
controls. Use the front panel voltage calibration marks
for an open circuit load and divide the values by two
when the PG 508 is operating into a 50 ( load. The
OUTPUT (VOLTS) controls are interlocked to prevent
setting the HIGH LEVEL more negative than the LOW
LEVEL. It is also impossible to set the controls for more
than about 20 V peak to peak output amplitude into an
open circuit or 10 V into 50 n.
Pulse amplitude always equals the pulse high level
minus the pulse low level. Offset may be the high level
or the low level, whichever is used as the base line
reference level. The flexibility of this method is useful in
certain applications such as logic testing. Either the high
or low level can be varied without disturbing the other.
Fig. 1-3 . Location for transition custom timing
capacitor .
The pulse high and low levels can be preset. Push
the PRESET button and adjust the HIGH LEVEL and the
LOW LEVEL potentiometers with a screwdriver for the
desired output levels.
External Triggering and Gating
To change the TRIG/GATE IN input impedance
remove the plug-in from the mainframe. Remove the
left side cover. Set the slide switch, located on the Input
board and labeled Input Impedance, to either the 50 n or
the 1 MO position. In the 1 MO position the shunt
capacitance is approximately 20 pF. A standard
oscilloscope probe can be used to acquire the triggering
signal from the external circuitry. If a compensated
probe is used, calibrate the probe on the input of a 1 M)
20 pF oscilloscope first. A 10X probe allows triggering
directly from high impedance sources such as MOS
digital circuitry with an effective TRIG/GATE LEVEL
range of ±30 V.
For external gating select the desired period and
duration. Press the SYNC GATE pushbutton. Select the
desired trigger slope with the + or - SLOPE button. The
OUTPUT now consists of pulses, described by the front
panel controls, whenever the TRIG/GATE IN input
exceeds the TRIG/GATE LEVEL control setting.
To externally trigger the PG 508, connect the
triggering signal to the TRIG/GATE IN connector. Select
the slope on which triggering is desired with the + or -
SLOPE button. Place the PERIOD switch in the EXT
TRIG OR MAN position. Now adjust the TR IG/GATE
LEVEL control for the desired triggering level. The
output waveform commences about 48 ns after the
triggering signal.
1-3
Summary of Contents for PG 508
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Page 51: ... BACKSIDE TRANSITION TIMING BOARD Α3 ...
Page 53: ...HIGH LOW LEVEL LEVEL Trigger Generator PG 508 ...
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Page 93: ...M30603 Change Reference DESCRIP riON LEVEL CONTROL MULTIPLIER Partial ...
Page 100: ...TM 11 6625 2980 14 Figure 1 0 Pulse generator AN USM 359A vi ...
Page 145: ...TM 11 6625 2980 14 POWER MODULE INTERFACE PIN ASSIGNMENTS FRONT VIEW A 15 ...
Page 146: ...TM 11 6625 298014 DETAILED BLOCK DIAGRAM A 16 ...
Page 165: ...TM 11 6625 2980 14 FO 2 Block Diagram 4 3 4 4 blank ...
Page 166: ...TM 11 6625 2980 14 FO 3 Input circuit schematic diagram 4 5 4 6 blank ...
Page 167: ...TM 11 6625 2980 14 FO 4 Period generator schematic diagram 4 7 4 8 blank ...
Page 168: ...TM 11 6625 2980 14 FO 5 Delay generator schematic diagram 4 9 4 10 blank ...
Page 170: ...TM 11 6625 2980 14 FO 7 Transition time generator schematic diagram 4 13 4 14 blank ...
Page 171: ...TM 11 6625 2980 14 FO 8 Level control multiplier schematic diagram 4 15 4 16 blank ...
Page 172: ...TM 11 6625 2980 14 FO 9 Output amplifier schematic diagram 4 17 4 18 blank ...
Page 173: ...TM 11 6625 2980 14 FO 10 Tracking voltage supply schematic diagram 4 19 4 20 blank ...
Page 174: ...TM 11 6625 2980 14 FO 11 PG 508 power supply schematic diagram 4 21 4 22 blank ...
Page 175: ...TM 11 6625 2980 14 FO 12 TM 503 power supply schematic diagram 4 23 4 24 blank ...
Page 176: ...TM 11 6625 2980 14 FO 13 A2 board component locations 5 3 5 4 blank ...
Page 177: ...TM 11 6625 2980 14 FO 14 A3 board component locations 5 5 5 6 blank ...
Page 178: ...TM 11 6625 2980 14 FO 15 A4 board component locations 5 7 5 8 blank ...
Page 179: ...TM 11 6625 2980 14 FO 16 PG 508 exploded view 5 9 5 10 blank ...
Page 180: ...TM 11 6625 2980 14 A 17 A 18 blank ...
Page 181: ...TM 11 6625 2980 14 TM 503 POWER MODULE A 23 A 24 blank ...
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