Theory of Operation
SPG 422 Service Manual (B034000 and above)
3–9
and U43. The video data with embedded audio exists from U45 on the SER
DIG[0..9] bus and enters into U44 as the serial data test signal, SDT[0..9]. There
the video stream splits in two. EDH data is embedded into one of the data
streams, scrambled, and exits U44 as the serial digital test signal, SDT[0..9]. The
other data stream is converted into a black signal, EDH data is embedded,
scrambled, and exits U44 as the serial digital black signal, SDB[0..9].
The Coprocessors are programmed by the microprocessor from the data stored in
U11 <1>. The audio data is a part of the data in EPROM, U10 <1>.
The serial black, SDB[0..9], and serial bars, SDT[0..9], signals are serializer by
U48 and U49, respectively. U47 and U46 are the Serial Output drivers for the
signals.
Genlock Type Selector 4:1 MUX
. Controlled by signals from the CPU, U50 selects
which type of genlock signal to expect. The selected signal is then converted to
VCO_TUNE and used as the correction signal for the VCXO.
13.5 MHz VCXO.
The heart of the VCXO is the Oven Oscillator Assembly. It takes
the VCXO correction signal and a reference voltage to produce the 13.5 MHz
instrument clock signal that is phase locked to the genlock input signal. The
13.5_OSC signal is this main reference clock signal. All other timing signals are
derived from this signal.
Any errors with the oscillator are flagged with LEDs. DS4 will light if the
VCO_TUNE signal is greater than its threshold level. This indicates that the
oscillator is not in its acceptable level. DS1 will light if the oscillator is under
temperature. The oscillator is not consider stable until this light goes out (after
an approximate 20-minute warm-up time).
Direct Digital Synthesizer.
The main purpose of the Direct Digital Synthesizer,
U82, is to produce the F
SC
clock for the Burst Lock circuit and the Edge Strobe
for the Sync Lock circuit.
The purpose of the 108 MHz oscillator is to step up the 13.5 MHz instrument
clock to produce the 27 MHz clock and the 108 MHz clock.
The 27 MHz clock is used by the Genlock Controller and DDS. The Fine Phase
and SCH measurement circuits use the 108 MHz.
DS2 lights if the 108 MHz loop is unlocked.
Fine Phase Control Signals.
U91 uses the change angle signals from the Genlock
Controller to generate clocks that are slightly off phase from the main 27 MHz
Serial Video Outputs <5>
13.5 MHz Genlock Control
<6>
108 MHz Oscillator <7>
Summary of Contents for SPG 422
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