Tektronix TSG 95 Service Manual Download

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Theory of Operation

3–2

TSG 95 Service Manual

The program memory is stored in the ROM (U24). The ROM is accessed with
the help of the ASIC. Since the lower address information and the data are multi-
plexed on port D of the

P, the ASIC is used to latch the lower eight bits of the

address. This lower address byte is available on pins AO7..AO0 of the ASIC.
The upper byte of the address comes from the

P port F. The ASIC also decodes

the address and the read, write, and address latch enable.

Ports A and B of U2 are used to interface with the keyboard (A2) through J2.
The keyboard is configured in a row and column format. The row lines are inputs
to U2 that are pulled up to +5 V by R2. A key press connects a row to a column.
U2 drives the column lines low (0 V) one by one; reading the row lines each time
to decode a key press. Only single key presses are decoded. If two or more keys
are pressed simultaneously they are ignored. U2 poles the keyboard every 25 ms
checking for key presses.

The upper two bits of port B are used to interface with a serial EEPROM (U4).
U4 contains stored IDs, user presets and power-up configuration information.
NVSCL is a serial clock generated by U2. NVSDA is a bi-directional serial data
bus. Information is passed from U2 to U4 through these lines.

Bit 5 of port B is used to toggle the watch dog (U23) input. U23 must be toggled
every 500 ms or it may reset the

P. U23 will also reset the

P if the power sup-

ply voltage drops below 4.5 V. When the instrument is powered up, U23 holds
the

P in reset until the power supply stabilizes.

Port C has several functions. Bits 3..0 are used as a 4-bit data bus. This bus is
used for communications with the LCD and a digitally controlled pot (EEPOT,
U16, A1

). The EEPOT is used to change the tone levels. Bits 6..4 are used

to control communications with the LCD. Bit 7 is used to control communica-
tions with the EEPOT.

Portions of the circuitry are also controlled by the

P via the ASIC. The ASIC

contains registers that can be written to that control output pins. An 8-bit port
labeled PORT1, and a 4-bit port labeled PORT2 are available. PORT1 bits 1..0
(AUDLAT, AUDSID) are used for communications with the tone chip (U12, A1

). Bit 2 (LCDBL) is used to turn the LCD backlight on and off. Bit 3

(PWRDN) is used to turn the instrument off through the power supply controller.
Bit 7 (DACGAIN) is used to change the gain of the DAC to adjust scaling for
PAL(HIGH) or NTSC(LOW) signals. PORT2 is used for turning the tone on and
off (AUDON), clicking the tone channels separately (ACH1_OFF and
ACH2_OFF), and attenuating the tone for a –10 dBu level (ANEG10DB).

There are also two pins that generate strobes when they are addressed. STRBHI
generates an active high strobe when addressed, and is used as the data clock
(AUDSCK) for the tone chip (U12, A1

). STRBLOW is an active low strobe

that is used to reset counters in the ASIC.

Two of the analog-to-digital converter (ADC) inputs on the

P are used. One

monitors the battery or input voltage (VIN). A resistive divider (R28 and R29)