© Teledyne UK Limited 2020
Document subject to disclaimer on page 1
A1A-795787 Version 1, page 5
ELECTRICAL INTERFACE
NOTES
8) All operating voltages are with respect to image clock low level (nominally 0V). To ensure correct device
operation, the drive circuitry must be designed so that any value in the range Min to Max can be set.
9)
φ
R high level is typically 1V above the high level of RØ1, RØ2 & RØ3.
10) See details of output circuit. Do not connect to voltage supply but use a
∼
5 mA current source or a
∼
5 k
Ω
external load. The quiescent voltage on OS is typically 5V more positive than that on RD. The current through
these pins must not exceed 20 mA. Permanent damage may result if, in operation, OS experiences short
circuit conditions.
11) Adjust to achieve full depletion, it should be noted that only very minimal study has been performed into the
depletion depth, so this voltage has not been optimised. Ensure that it is initially equal to 0V at power up and
then ramped between an upper limit of +FSS and a minimum (i.e. greatest negative) value where point spread
function (or MTF) shows no further improvement or where the current in BSS increases to ~1µA. If this voltage
is too large then some increase in white defects may be seen, and so there can be a trade-off between this
effect and of optimum PSF.
12) May need to be adjusted in conjunction with BSS voltage to minimise leakage currents.
13) There is an interdependence between the FSS, BSS, image section voltages and line transfer time. If one of
these parameters is changed then it is often required to change one of the others.
14) If all voltages are set to the ‘typical’ values, operation at or close to specification should be obtained. Some
adjustment within the minimum – maximum range specified may be required to optimise performance.
PIN REF
DESCRIPTION
CLOCK AMPLITUDE OR DC
LEVEL (V) (see note 8)
MAX RATINGS
with respect to
FSS
Notes
Min
Typical
Max
1
FSS
Front Substrate
+
7
+7.5
+
11
N/A
13
2
IØ3
Image Clock High
+12
+15
+16
±20
13
Image Clock Low
-0.5
0
+0.5
±20
3
IØ2
Image Clock High
+12
+15
+16
±20
13
Image Clock Low
-0.5
0
+0.5
±20
4
IØ1
Image Clock High
+12
+15
+16
±20
13
Image Clock Low
-0.5
0
+0.5
±20
5
BSS
Back Substrate
-
0
FSS
11, 13
6
ØR
Reset Clock High
+8
+12
+15
±20
9
Reset Clock Low
-0.5
0
+1.5
±20
7
RØ3
Register Clock High
+8
+12
+15
±20
Register Clock Low
-0.5
0
+1.5
±20
8
RØ2
Register Clock High
+8
+12
+15
±20
Register Clock Low
-0.5
0
+1.5
±20
9
RØ1
Register Clock High
+8
+12
+15
±20
Register Clock Low
-0.5
0
+1.5
±20
10
N/C
Not Connected
-
N/A
11
N/C
Not Connected
-
N/A
12
OG
Output Gate
+1
+3
+5
±20
13
OS
Output Source
N/A
-0.3 to +35
10
14
OD
Output Drain
+27
+31
+32
-0.3 to +35
15
RD
Reset Drain
+15
+18
+19
-0.3 to +35
16
FSS
Front Substrate
+
7
+7.5
+
11
N/A
13
17
SW
Summing Well Clock High
+8
+12
+15
±20
Summing Well Clock Low
-0.5
0
+1.5
±20
18
GD
Guard Drain
+27
+30
+32
-0.3 to +35
12
19
SG
Spare Gate
0
0
+5
±20
20
BSS
Back Substrate
-10
0
FSS
-25 to +0.3
11, 13