© Teledyne UK Limited 2020
Document subject to disclaimer on page 1
A1A-795787 Version 1, page 8
DETAIL OF OUTPUT CLOCKING
CLOCK TIMING REQUIREMENTS
Symbol Description
Min
Typ
Max
Unit
T
p
Image clock period
3000
3250
Note 15
µ
s
T
i
Line transfer Time
-
4510
Note 15
µ
s
t
wi
Image clock pulse width
1500
1800
Note 15
µ
s
t
oi
Image clock pulse overlap
400
500
-
µ
s
t
li
Image clock pulse, two phase low
400
500
Note 15
µ
s
t
dir
Delay time, IØ stop to RØ start
5
20
Note 15
µ
s
t
dri
Delay time, RØ stop to IØ start
5
20
Note 15
µ
s
T
r
Output register clock cycle period
1
2
Note 16
µ
s
t
rr
Register pulse rise time (10 to 90%)
50
90
Note 17 ns
t
fr
Register pulse fall time (10 to 90%)
50
90
Note 17- ns
t
or
Register pulse overlap (50%)
20
120
Note 17- ns
t
wx
Reset pulse width
30
170
Note 17- ns
t
rx
Reset pulse rise and fall times
20
80
Note 17- ns
t
dx
Delay time, ØR low to RØ3 low
-
80
Note 17- ns
15) No maximum other than that necessary to achieve an acceptable dark signal at longer readout times and
general compliance to the line transfer timing diagram. Scale to T
p
.
16) Determined by readout time requirement.
17) Scale to T
r
.
