Programming Manual
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T3AWG3K-C Series Arbitrary Waveform Generator
True-Arb Operating Mode
23
•
Operation Event Register (OEVR)
•
Operation Enable Register (OENR)
These registers are made up of the same bits defined in the following table. Use the STA-
Tus:OPERation commands to access the operation status register set.
2.2.5.1
Operation Condition Register (OCR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
WFT
--
--
--
Table 12: Operation Condition Register (OCR)
Bit3 Waiting for trigger (WFT): indicates that the instrument is waiting for a trigger event to oc-
cur.
When the specified state changes in the OCR, its bit is set or reset. This change is filtered with
a transition register, and the corresponding bit of the OEVR is set.
If the bit corresponding to the event has also been set in the OENR, the SBR OSS bit is also set.
2.2.6
Questionable status block
The questionable status register set contains bits which give an indication of the quality of
various aspects of the signal together with the fanned out registers as described in the next
subsections. It consists of the following registers:
•
Questionable Condition Register (QCR)
•
Questionable Event Register (QEVR)
•
Questionable Enable Register (QENR)
Despite the commands to query these registers are usable (see STATus:QUEStionable com-
mands) , these register are not used in this version.