S50 Hardware User Guide
1VV0301505 Rev. 3
Page 28 of 60
2021-05-05
Not Subject to NDA
5.2.
Pin Description
Pin Name
Signal
Alternate
Type
(1)
Act
nRF52
Description
E6
F6
VSUP1
PWR
VDD
+3,0V nom.
A7
B[5-8]
C[5-8]
D8
E7
E8
F7
F8
GND
PWR
VSS
Ground
All GND pins must be connected
A8
ANT PIN
RF
RF
AI: not connected
AP: RF output (50
Ω
)
A3
NFCANT1
RF
P0.09
NFC-Antenna
A4
NFCANT2
RF
P0.10
NFC-Antenna
F1
TESTMOD
E#
I-PU
(3)
L
P0.08
Enable Testmode
E1
BOOT0
I-PD
(3)
P0.25
Startup with Bootloader
E3
SWDIO
I/O-PU
SWDIO
Serial Wire Debug (data)
D6
SWCLK
I-PD
SWCLK
Serial Wire Debug (clock)
B1
EXT-RES#
I-PU
L
P0.21
User Reset
A6
XL-IN
I/O
P0.00
XTAL 32,768kHz input
A5
XL-OUT
I/O
P0.01
XTAL 32,768kHz output
F4
UART-TXD
O-PP
P0.17
Serial Data OUT
D2
UART-
RXD
I
P0.11
P0.13
Serial Data IN
D7
UART-
RTS#
O-PU
L
P0.07
Flow Control/IUC
(internally connected to a 470k
pull up)
F3
UART-
CTS#
I-PD
(4)
L
P0.12
Flow Control/IUC
B4
IUR-OUT#
O-PP
(4)
L
P0.04
UICP Control
D5
IUR-IN#
I-DIS
(4)
L
P0.29
UICP Control
D3
GPIO[0]
I2C-SCL
I/O
P0.27
GPIO
(2)
B2
GPIO[1]
AIN,
I2C-SDA
I/O
P0.31
GPIO
(2)
D1
GPIO[2]
SPI-MOSI
I/O
P0.14
GPIO
(2)
E4
GPIO[3]
AIN
I/O
P0.02
GPIO
(2)
D4
GPIO[4]
AIN
I/O
P0.30
GPIO
(2)
F2
GPIO[5]
AIN,
SPI-MISO
I/O
P0.05
GPIO
(2)
C4
GPIO[6]
AIN
I/O
P0.03
GPIO
(2)
C3
GPIO[7]
AIN
I/O
P0.28
GPIO
(2)
E2
GPIO[8]
SPI-SCK
I/O
P0.06
GPIO
(2)
A2
GPIO[9]
I/O
P0.18
GPIO
(2)
A1
GPIO[10]
I/O
P0.22
GPIO
(2)
B3
GPIO[11]
I/O
P0.20
GPIO
(2)
E5
GPIO[12]
I/O
P0.16
GPIO
(2)
C2
GPIO[13]
I/O
P0.15
GPIO
(2)
F5
GPIO[14]
I/O
P0.26
GPIO
(2)
C1
NC
not connected
(1)
PWR: Power; I: Input; O: Output; I/O: bidir; PU: pull-up; PD: pull-down; DIS: disconnected; PP: push-pull; RF:
RadioFreq
(2)
Pin function depends used firmware, refer to 5.3