JF2 Hardware User Guide
1vv0300985 Rev.4 2013-04-09
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
Page 12 of 40
Mod. 0805 2011-07 Rev.2
VDD 18
ON-OFF
SYSTEM-ON
(clock runs)
Unknown
Unknown
D
T
1
D
T
2
D
T
HIGH
RTC CLK
(INTERNAL)
Figure 1 – Initial Application of Main Power
Timed
Parameter
Prior
Event/State
Symbol
Min
Typ
Max
Unit
RTC startup time
First power
applied
1
0
299
1000
ms
FSM Ready pulse
RTC running
2
10
T
RTC
Min ON-OFF high
HIGH
3
T
RTC
T
RTC
is equivalent to one RTC (32.678KHz) clock cycle.
Table 1 – Power State Timing
The host system can determine if the J-F2 is “ready” as follows
A short pulse on SYSTEM_ON output line indicates to a host that the J-F2 is ready and armed to
accept an ON_OFF pulse.
The host can wait a fixed duration. Wait at minimum 5 seconds before sending an ON_OFF pulse.
Note that Telit recommends monitoring SYSTEM_ON.
The host can issue ON_OFF pulses repeatedly every 100ms and monitor for JF-2 SYSTEM_ON
output to go HIGH. Note that issuing an ON_OFF pulse once the system is running may cause the
firmware to initiate the shutdown process
The host can issue ON_OFF repeatedly every one second and wait for serial messages to be output
within the one second. Note that issuing an ON_OFF pulse once the system is running may cause the
firmware to initiate the shutdown process