Terasic ALTERA ICB HSMC, User Manual

Page 1: ...1 ...

Page 2: ...xpansion Connector 9 3 2 GPIO Interface 12 3 3 RS 232 Interface 13 3 4 RS 485 Interface 14 3 5 CAN Interface 16 3 6 PIO Interface 16 Chapter 4 Assembling the ICB 18 4 1 Assemble ICB with DE2 115 18 4 2 Generate ICB Project via DE2 115 System Builder 19 Chapter 5 ICB Demonstrations 25 5 1 System Requirements 25 5 2 RS 232 Communication 25 5 3 RS 485 Loopback Test 27 5 4 CAN Loopback Test 29 Chapter...

Page 3: ...2 6 1 Revision History 32 6 2 Copyright Statement 32 ...

Page 4: ...ication network for industrial use through the industrial standard interfaces on the ICB This board features one RS 232 interface one GPIO interface four RS 485 interfaces two CAN interfaces and four PIO interfaces The ICB is an ideal addition to the DE2 115 platform for developing industrial networking solutions on Altera FPGAs 3 1 1 1 1 Features Features Figure 1 1 shows a photograph of the ICB ...

Page 5: ...ivers two channels output with DB9 female connectors and 10 pin headers share pins with DB9 two channels output with 10 pin headers CAN interface o Maxim Low Supply Current CAN transceiver MAX3051 o High speed operation up to 1Mbps o 2 male DB9 and two 10 pin headers share pins with Connectors Power o Isolated 5V power supply for RS 485 transceiver bus side o 5V 3 3V power supply 1 2 1 2 About the...

Page 6: ...Figure 1 2 ICB contents 5 1 3 1 3 Getting Help Getting Help Here is information of how to get help if you encounter any problems Terasic Technologies Tel 886 3 550 8800 Email support terasic com ...

Page 7: ...diagram and components 6 2 1 2 1 Layout and Components Layout and Components The picture of the ICB is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components Figure 2 1 The ICB HSMC PCB and component diagram top view ...

Page 8: ...IO Header J3 6 pin Header JP1 JP6 12 pin Header JP7 10 pin Header JP2 JP3 JP4 JP5 JP6 JP9 JP10 DB9 Connector J1 J2 J4 J5 J6 7 2 2 2 2 Block Diagram of the ICB Block Diagram of the ICB Figure 2 3 shows the block diagram of the ICB HSMC The HSMC connector houses all the wires from peripheral interfaces and makes to the FPGA on the main board ...

Page 9: ...Figure 2 3 Block diagram of ICB HSMC 8 ...

Page 10: ...tions on HSMC connector Pin Numbers Name Direction Description 1 32 33 HSMC_SDA Input Output HSMC serial address data I O 34 HSMC_SCL Output HSMC serial clock 35 HSMC_TCK Output JTAG clock 36 HSMC_TMS Output JTAG mode select 37 HSMC_TDO Input JTAG test data out 38 HSMC_TDI Output JTAG test data in 39 40 41 GPIO_DATA34 Input Output GPIO data 42 GPIO_DATA33 Input Output GPIO data 43 GPIO_DATA35 Inpu...

Page 11: ...1 Input Output GPIO data 74 GPIO_DATA17 Input Output GPIO data 75 VCC3P3 Power Power 3 3V 76 VCC12 Power Power 12V 77 GPIO_DATA22 Input Output GPIO data 78 GPIO_DATA18 Input Output GPIO data 79 GPIO_DATA23 Input Output GPIO data 80 GPIO_DATA19 Input Output GPIO data 81 VCC3P3 Power Power 3 3V 82 VCC12 Power Power 12V 83 GPIO_DATA28 Input Output GPIO data 84 GPIO_DATA24 Input Output GPIO data 85 GP...

Page 12: ...2_DATA3 Input Output PIO2 data 123 VCC3P3 Power Power 3 3V 124 VCC12 Power Power 12V 125 RS485_2_RXD Input RS 485 channel 2 RXD 126 RS485_0_RXD Input RS 485 channel 0 RXD 127 RS485_2_TXD Output RS 485 channel 2 TXD 128 RS485_0_TXD Output RS 485 channel 0 TXD 129 VCC3P3 Power Power 3 3V 130 VCC12 Power Power 12V 131 RS485_2_RTS Output RS 485 channel 2 RTS 132 RS485_0_RTS Output RS 485 channel 0 RTS...

Page 13: ...9 VCC3P3 Power Power 3 3V 160 GND Power Power Ground 12 3 2 3 2 GPIO Interface GPIO Interface This section describes the GPIO interface on the ICB The ICB contains a GPIO interface with a 40 pin header Figure 3 1 shows the pin names defined on the GPIO connector used in general purpose applications For pin mapping information between the GPIO and HSMC connector please refer to Table 3 1 using pin ...

Page 14: ... diodes and one serial resistor Figure 3 2 shows the protection circuitry that is on each of the 36 data pins on the 40 pin header Figure 3 2 Protection circuit for data pins on GPIO 13 3 3 3 3 RS 232 Interface RS 232 Interface This section describes the RS 232 interface on the ICB HSMC The ICB provides a full featured RS 232 interface using a Maxim 3238 chip with a guaranteed data rate of 250 Kbp...

Page 15: ...terface This section describes RS 485 interface on the ICB HSMC There are four RS 485 links from the HSMC connector to two female DB9 connectors and four 10 pin headers Two of the 10 pin headers share pins with the two DB9 connectors Within the four ports two ports are compliant with the profibus specification and are suitable of using as physical link in industrial multi terminal control applicat...

Page 16: ...485_0_B 6 JP3 8 J2 RS485_0_RTS_CON 7 JP3 4 J2 VCC5_ISO 2 JP3 6 J2 Channel 0 Profibus compliance GND 9 JP3 5 J2 RS485_1_A 6 JP2 8 J1 RS485_1_B 5 JP2 3 J1 RS485_1_RTS_CON 7 JP2 4 J1 VCC5_ISO 2 JP2 6 J1 Channel 1 GND 9 JP2 5 J1 RS485_2_A 5 JP5 RS485_2_B 6 JP5 RS485_2_RTS_CON 7 JP5 VCC5_ISO 2 JP5 Channel 2 Profibus compliance GND 9 JP5 RS485_3_A 6 JP4 RS485_3_B 5 JP4 RS485_3_RTS_CON 7 JP4 VCC5_ISO 2 J...

Page 17: ...pin headers and DB9 connectors for CAN signals Table 3 3 Pin assignments and descriptions for CAN interfaces CAN Channel Signal Name 10 pin Header DB9 Connector CANH 4 JP10 7 J6 CANL 3 JP10 2 J6 Channel 0 GND 2 5 JP10 3 5 6 J6 CANH 4 JP9 7 J5 CANL 3 JP9 2 J5 Channel 1 GND 2 5 JP9 3 5 6 J5 3 6 3 6 PIO Interface PIO Interface This section describes the PIO interface on the ICB HSMC The board has fou...

Page 18: ...Figure 3 6 Wiring between HSMC and PIO interface 17 ...

Page 19: ...ocket JP8 of the DE2 115 board Users could additionally screw on and tighten the connection for extra mechanical stability Figure 4 1 shows the assembled hardware Figure 4 1 Assembling ICB with DE2 115 board Note that the ICB is designed to use the 3 3V or 2 5V I O signaling standard Before powering on the DE2 115 board set the desired I O standard for the HSMC connector Figure 4 2 shows the heade...

Page 20: ...utomatically generated top level design and Quartus II setting file eliminate potential common mistakes encountered when manually typing in the signal wires between DE2 115 and daughter card Install and launch the DE2 115 System Builder The DE2 115 System Builder is available from the DE2 115 system CD ROM under the DE2_115_tools folder Users can copy the entire folder to a host PC without install...

Page 21: ...DE2 115 System Builder window Input Project Name Input project name as show in Figure 4 4 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity 20 ...

Page 22: ...Configuration users can enable the desired components on the FPGA host board as shown in Figure 4 5 If the component is enabled the DE2 115 System Builder will automatically generate the associated pin assignments including the pin names pin locations pin directions and I O standards 21 ...

Page 23: ...ation Group HSMC Expansion Figure 4 6 illustrates the usage of the DE2 115 System Builder specifying ICB connecting to the HSMC interface This will automatically generate wiring connections between the host board and ICB HSMC 22 ...

Page 24: ... Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty Figure 4 7 illustrates the generated top level design file contains information on the ICB HSMC connections 23 ...

Page 25: ...Figure 4 7 Top level design file includes ICB HSMC information 24 ...

Page 26: ... RS 232 Communication RS 232 Communication This demonstration illustrates how to construct a communication channel between a PC and RS 232 port on the ICB card Set up of the RS 232 port as follows Baud rate 9600 bps Data bits 8 bits Stop bit none Parity check bit 1 bit The demonstration also provides PC side UART terminal communication software using the above parameters The software running on th...

Page 27: ...2 115 board The green LED D40 near the HSMC connector will indicate a valid connection Connect the DE2 115 to the PC using the USB Blaster cable and then run the demo batch DE2_115_ICB_RS232 bat under the Demonstrations DE2_115_ICB_RS232 demo_ batch folder Connect the RS 232 port on the ICB to the PC using a DB9 female to female cross cable Tx and Rx lines are cross connected on two headers to for...

Page 28: ...ith its content set by SW7 0 through channel 0 Once the data is received by the RS 485 controller on channel 1 side software will set channel 1 on transmit state and channel 0 on receive state then sends data back to the loop The RS 485 controller on channel 0 side finally gets the passed back data and compares it to the original data The same procedure will be carried out for channel 2 and 3 exce...

Page 29: ...iring diagram for two loops Power on DE2 115 board Validate the connection by examining the status of the green LED near the HSMC connector Change the transmit contents by setting the values of SW7 0 for loop pair 1 channel 0 and 1 SW15 8 for loop pair 2 channel 2 and 3 Connect the DE2 115 to the PC using USB Blaster cable and execute DE2_115_ICB_RS485 bat under the Demonstrations DE2_115_ICB_RS48...

Page 30: ...w to construct a communication loop between two CAN interfaces where one initiates the data transfer and the other receives data then sends it back to the loop SW7 0 is used to set up the transmit data contents The data loopback flow for CAN is the same as RS 485 In this demonstration the Nios II processor in the FPGA on the DE2 115 board takes charge of the control work and gives the test result ...

Page 31: ...elf Demonstration setup Connect ICB to DE2 115 Connect H and L wire of CAN 0 and CAN1 respectively Figure 5 7 shows the wiring manner for the CAN loopback test Power on DE2 115 board Validate the connection by examining the status of the green LED near the HSMC connector Set the transmitting data for the loop by toggling SW7 0 Execute the DE2_115_ICB_CAN bat in the Demonstrations DE2_115_ICB_CAN d...

Page 32: ... for CAN loopback test Figure 5 8 Prompt information while running the test Table 5 2 Loopback test result on HEXs for CAN Test Pass Info Test failed info S test data FAIL test data represents the value set by SW7 0 31 ...

Page 33: ... Appendix 32 6 1 6 1 Revision History Revision History Version Change Log V1 0 Initial Version Preliminary 6 2 6 2 Copyright Statement Copyright Statement Copyright 2010 Terasic Technologies All rights reserved ...