Board Components
15
150
SFP7_MOD2_SDA
Inout
SDA Serial Data Signal
151
SFP7_MOD1_SCL
Output
SCL Serial Clock Signal
152
SFP7_MOD0_PRSNTn Input
LED
indicator that the module is present
153
3V3 Power
Power
3.3V
154
12V Power
Power
12V
155
SFP7_RATESEL Output
Rate
Select
156
CLK2_p Input
Differential
Clock
Input
157
SFP7_LOS
Input
Receiver Loss of Signal Indication
158
CLK2_n Input
Differential
Clock
Input
159 N.C. N/A
Not
Connect
160
GND Power
Power
Ground
3.2
3.2 Clock Circuitry
This section describes the board’s clock inputs and outputs
LVDS clock frequencies of 61.44MHz, 125MHz, 155.52MHz, or 156.25MHz can be selected for HSMC
CLK1p/CLK1n. CLK1p/CLk1n will be converted to a single-ended clock signal and output to an SMA.
LVDS clock frequencies of 125MHz, 155.52MHz, 156.25MHz, or SMA_CLKp/n can be selected for HSMC
CLK2p/CLK2n pins. CLK2p/CLK2n will also be output directly to SMAs.
CLK_IN is a single-ended CMOS signal received by the daughter card from the FPGA and is cleaned-up with
a frequency synthesizer. The cleaned-up clock is output to an LVPECL SMA pair.
