71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 37 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
The mass erase sequence is:
1. Write 1 to the
FLSH_MEEN
bit (SFR address 0xB2[1].
2. Write pattern 0xAA to
FLSH_ERASE
(SFR address 0x94)
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to
FLSH_PGADR
(SFR address 0xB7[7:1]
2. Write pattern 0x55 to
FLSH_ERASE
(SFR address 0x94)
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user. The I/O RAM
register
FLSH_PWE
(flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM writes. Before setting
FLSH_PWE
, all interrupts need to be disabled by setting EAL =1.
Note: Flash write operations in the range 0x2000 to 0x20FF will also affect the I/O RAM. Thus, flash writes to this range
have to be either avoided (code must jump around the affected range), or they must contain the data that the I/O RAM
expects.
MPU RAM
: The 71M6403 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256-
bytes of internal RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.
CE Data RAM:
The CE DRAM is the data memory of the CE. The MPU can read and write the CE DRAM as the primary means
of data communication between the two processors.
CE Program RAM:
The CE PRAM is the program memory of the CE. The CE PRAM has to be loaded with CE code before the
CE starts operating. CE PRAM cannot be accessed by the MPU when the CE is running.
Real-Time Clock (RTC)
The RTC is driven directly by an external clock signal provided at the CK38 pin. In the absence of the 3.3V supply, the RTC is
powered by the external battery (VBAT pin). The RTC consists of a counter chain and output registers. The counter chain
consists of seconds, minutes, hours, day of week, day of month, month, and year. The RTC is capable of processing leap years.
Each counter has its own output register. Whenever the MPU reads the seconds register, all other output registers are
automatically updated. Since the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register multiple
times until two consecutive reads are the same (requires either 2 or 3 reads). At this point, all RTC output registers will have the
correct time. Regardless of the MPU clock speed, RTC reads require one wait state.
The RTC interrupt must be enabled using the I/O RAM register
EX_RTC
(address 0x2002[1]). RTC time is set by writing to the
I/O RAM registers
RTC_SEC
,
RTC_MIN,
through
RTC_YR
. Each byte written to RTC must be delayed at least 3 CK38 cycles
from any previous byte written to the RTC.
The RTC counter chain is designed for use with a 32.768 kHz clock source. The 71M6403 requires a 19.6608 MHz master
clock for proper CE filter operation. The external (low cost) ‘HC4040 counter generates an approximate clock frequency for the
RTC. The ‘HC4040’s divide-by-512 output provides a 38.4 kHz clock signal. Therefore, the RTC runs about 17% faster using
the ‘HC4040. A divide-by-600 would generate the ideal 32.768 kHz clock from the 19.6608 MHz oscillator. Alternatively, a
32.768 kHz clock can be sourced independently from the system.
Two time-correction bits, the I/O RAM registers
RTC_DEC_SEC
(0x201C[1]) and
RTC_INC_SEC
(0x201C[0]) are provided to
adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second at
the next update of the
RTC_SEC
register. Thus, if the temperature coefficient of the clock source at the CK38 pin is known, the
MPU firmware can integrate temperature and correct the RTC time as necessary as discussed in temperature compensation.
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