71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 56 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
OPT_TXDIS
2008[5]
R/W Tristates the OPT_TX output.
PREBOOT
SFR B2[7]
R
Indicates that the preboot sequence is active.
Reserved[1:0]
2001[7:6] R/W
Reserved
RTM_EN
2002[3]
R/W Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2060
2061
2062
2063
R/W Four RTM probes. Before each CE code pass, the values of these
registers are serially output on the RTM pin. The
RTM
registers are
ignored when
RTM_EN
=0.
SECURE
SFR B2[6]
R/W Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
SSI_EN
2070[7]
R/W Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SEG5 pins. If
SSI_RDYEN
is set, SEG6 is enabled also. The pins take
on the new functions SCLK, SSDATA, SFR, and SRDY, respectively.
When
SSI_EN
is high and
LCD_EN
is low, these pins are converted to
the SSI function, regardless of
LCDEN
and
LCD_NUM
. For proper
LCD operation,
SSI_EN
must not be high when
LCD_EN
is high.
SSI_10M
2070[6]
R/W SSI clock speed: 0: 5MHz, 1: 10MHz
SSI_CKGATE
2070[5]
R/W SSI gated clock enable. When low, the SCLK is continuous. When
high, the clock is held low when data is not being transferred.
SSI_FSIZE[1:0]
2070[4:3]
R/W SSI frame pulse format:
0: once at beginning of SSI sequence (whole block of data),
1: every 8 bits, 2: every 16 bits, 3: every 32 bits.
SSI_FPOL
2070[2]
R/W SFR pulse polarity: 0: positive, 1: negative
SSI_RDYEN
2070[1]
R/W SRDY enable. If
SSI_RDYEN
and
SSI_EN
are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SSI_RDYPOL
2070[0]
R/W SRDY polarity: 0: positive, 1: negative
SSI_BEG[7:0]
SSI_END[7:0]
2071[7:0]
2072[7:0]
R/W The beginning and ending address of the transfer region of the CE
data memory. If the SSI is enabled, a block of words starting with
SSI_BEG
and ending with
SSI_END
will be sent.
SSI_END
must be
larger than
SSI_BEG
. The maximum number of output words is limited
by the number of SSI clocks in a CE code pass—see
FIR_LEN,
MUX_DIV,
and
SSI_10M
.
Reserved
2001[5:0] R/W
Reserved
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