TPMC533 User Manual Issue 1.0.1
Page 71 of 107
3.2.1.10
Other Registers
3.2.1.10.1 Global Configuration Register (0x398)
Bit
Symbol
Description
Access
Reset
Value
31:2
-
Reserved
-
-
1
IRQ_ACK_CONF
Interrupt Acknowledge Configuration
0: Interrupts are acknowledged by writing ‘1’ to the
appropriate bit in the Interrupt Status Register
1: Interrupts are cleared when the Interrupt Status Register
is read
R/W
0
0
DMA_ENDIAN_CONF
DMA Endian Configuration
Sets the Endian Mode for DMA access to Host RAM.
0: Little Endian Mode (16bit digital values are stored in Little
Endian format in Host RAM)
1: Big Endian Mode (16bit digital values are stored in Big
Endian format in Host RAM)
R/W
0
Table 3-69: Global Configuration Register