2.2
Signal Conditioning Power Connector
3
Serial EVM Sites
3.1
Serial Digital I/O Connections
3.2
Chip Select, Frame Sync and Interrupt Options
www.ti.com
Serial EVM Sites
The Interface Board provides a common power bus to both signal conditioning sites. The power connector
used on the Interface Board is a 6-pin male header. Four power connectors JP1, JP2, JP3, and JP4 are
provided—each with the same pinout. This allows an analog-to-digital (ADC) converter to use the same
signal conditioning board as a digital-to-analog (DAC) converter, simply by rotating the signal conditioning
board 180 degrees.
shows the power connector voltages supplied to the signal conditioning module.
Table 3. Signal Conditioning Power Connections—JP1, JP2, JP3, and JP4
Signal
Pin Number
Signal
+VA
1
2
-VA
+5VA
3
4
-5VA
AGND
5
6
AGND
The serial interface consists of two digital I/O connectors (J15 and J16), two power connectors (JP5 and
JP6), and two analog I/O connectors (J10 and J12). The analog I/O connectors are configured as pass
through connections from/to the signal conditioning sites. See
for more information.
The serial site digital I/O connectors are 20-pin headers that provide access to the serial interface signals
defined in the TMS320 Cross-Platform Daughtercard Specification (
). These signals are based
on the multichannel buffered serial port (McBSP) interface found on most Texas Instruments DSPs.
shows the standard serial connector pinout.
Table 4. Digital I/O Connections—J15 and J16
Signal
(1)
Signal
(1)
Pin Number
Site 1 (J15)
Site 2 (J16)
Site 1 (J15)
Site 2 (J16)
DC_CNTLa
DC_CNTLb
1
2
TP Access
TP Access
DC_CLKXa
DC_CLKXb
3
4
DGND
DGND
DC_CLKRa
DC_CLKRb
5
6
TP Access
TP Access
DC_FSXa
DC_FSXb
7
8
TP Access
TP Access
DC_FSRa
DC_FSRb
9
10
DGND
DGND
DC_DXa
DC_DXb
11
12
TP Access
TP Access
DC_DRa
DC_DRb
13
14
TP Access
TP Access
EVM_INTa
EVM_INTb
15
16
TP Access
TP Access
DC_TOUTa
DC_TOUTb
17
18
DGND
DCND
TP Access
TP Access
19
20
TP Access
TP Access
(1)
Revision B boards include 470-
Ω
pulldown resistors at all points listed as TP Access via 6-position slide switches SW1 and
SW2.
DC_CNTLa and DC_CNTLb are routed directly to pin 1 of the Digital I/O connectors (J15 and J16
respectively) on Revision A Interface Boards. Revision B interface boards include jumpers W12 and W13
which apply the DC_CNTLx signal (default) or digital ground (shunt pins 2-3) to pin 1 of the digital I/O
connectors.
SLAU104C – May 2004 – Revised March 2009
List of Tables
3
