Software Control
ADC34JXX Tab
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Disable Dither CHA – disables the dither circuit if asserted, dither is on by default
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Disable Dither CHB – disables the dither circuit if asserted, dither is on by default
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Disable Dither CHC – disables the dither circuit if asserted, dither is on by default
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Disable Dither CHD – disables the dither circuit if asserted, dither is on by default
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CHA PwDn – power down CHA
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CHB PwDn – power down CHB
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CHC PwDn – power down CHC
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CHD PwDn – power down CHD
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CHA Gain Enable – enable the digital gain block for CHA
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CHB Gain Enable – enable the digital gain block for CHB
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CHC Gain Enable – enable the digital gain block for CHC
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CHD Gain Enable – enable the digital gain block for CHD
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Gain CHA – digital gain setting from 0 dB to 6 dB
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Gain CHB – digital gain setting from 0 dB to 6 dB
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Gain CHC – digital gain setting from 0 dB to 6 dB
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Gain CHD – digital gain setting from 0 dB to 6 dB
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Enable Test Pattern – enable the use of test patterns instead of sample data
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Align Test Data – align all test data on the outputs
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Test Pattern CHA – different available test patterns
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Test Pattern CHB – different available test patterns
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Test Pattern CHC – different available test patterns
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Test Pattern CHD – different available test patterns
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Custom Pattern – 14-bit custom bit pattern to be used when
Custom Pattern
is selected
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SerDes Test Pattern – available test patterns at the SerDes block
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Idle Sync Pattern – pattern used for SYNC request (K28.5 default)
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Test Mode Enable – option to enable long test pattern as per clause 5.1.6.3
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Flip ADC Data – normal operation is LSB first, enable for MSB first
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Insert Lane Alignment Chars – option to insert lane alignment chars as per clause 5.3.3.4
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TX Link Config – option to disable ILA when SYNC is de-asserted
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Ctrl K – default is 9 (20x mode), enable to use 0x31 for control
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Ctrl F – default is 2 (20x mode), enable to use 0x30 for control
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Scramble EN – optional scrambler
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Subclass – select subclass, default subclass 2
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Generate SYNC Request – generate Sync request
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JESD Buffer Output Current – change output buffer current, default 16 mA
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Link Layer RPAT – change running disparity in RPAT pattern test mode
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Link Layer Test Mode – generate test pattern per clause 5.3.3.8.2
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Pulse Detect Modes – select different pulse detection for SYSREF and SYNC
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Force LMF count – force LMF count
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LMF Count INIT – LMF count INIT
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Release ILA SEQ – delay generation of ILA sequence by 0, 1, 2, 3 MF after CGS
19
SLAU579A – June 2014 – Revised September 2014
ADC3xxx, ADC3xJxx EVM User’s Guide
Copyright © 2014, Texas Instruments Incorporated
