Quick Start Guide
4
SLAU620A – April 2016 – Revised May 2016
Copyright © 2016, Texas Instruments Incorporated
ADC32RF45/RF80 EVM Quick Startup Guide
2
Quick Start Guide
The EVM test procedure to obtain a valid data capture from the ADC32RF45 EVM using the
TSW14J56EVM capture card is provided in this section. This is the starting point for all evaluations.
2.1
Introduction
The ADC32RF45/RF80 EVM includes the ADC32RF4x or ADC32RF80 analog-to-digital converter with
JESD204B interface, and the LMK04828 clock chip to generate the device clock and SYSREF to the
ADC. Also included on the EVM is the optional LMX2582 or LMX2592 clock synthesizer device. Jumpers
and solder options on the EVM allow selection of the ADC sample clock from the LMX2582, the
LMK04828, or from a transformer-coupled external SMA input. The default assembly option is the
transformer-coupled external clocking option as set by jumper JP3. The EVM has an FMC connector
suitable for connection to readily-available FPGA development boards or to the TSW14J56 capture card.
The FPGA on the capture card also requires a device clock and SYSREF signal and the LMK04828 clock
device also supplies these signals to the FMC connector for that purpose.
This document is meant to convey all information needed to bring up the ADC32RF4x/RF80 EVM and
TSW14J56 capture card and get valid data capture with a good FFT result.
The JESD204B interface requires a number of important parameters to be decided in advance of setting
up the data link, such as, number of lanes, number of converters, number of samples per frame, and a
value K number of frames per multi-frame, among other parameters. Both sides of a JESD204B link must
be set up with the same values for all these parameters or else the FPGA that receives the data will not
be able to establish a synchronized link.
Getting these parameters inconsistent between ADC and
FPGA is perhaps the biggest single reason for an EVM setup to not function as expected.
The GUI
installers that come with the ADC32RF4x/RF80 and the TSW14J56 come with configuration files that are
meant to enable quick initial setup of a number of basic configurations. TI
strongly
suggests setting up
the EVM and capture card with a configuration described in this document and getting a working setup
before modifying the configuration to be closer to what the end-application requires. In this way the user
can know that the hardware is functioning, and that there is a working configuration that they can go back
to in the event of difficulty developing their own configuration.
The HSDC Pro GUI that comes with the TSW14J56 requires initialization files for both the decimation and
mixer logic (called Digital Down-Convert (DDC)) that the ADC32RF80 supports and the non-decimated full
rate mode called LMF82820 or 5-sample mode. (LMF82820 mode means that there are 8 lanes in use for
2 channels of ADC, with 8 octets of information on each lane per frame, for 20 samples of data per frame
per channel. That is equivalent to 5 samples per lane per frame, hence the mode being called 5 sample
mode. 5 samples per lane times 8 lanes is 40 samples, or 20 samples per channel. This mode is
sometimes called bypass mode because the decimation and mixer logic is bypassed in favor of full rate
output.) These ini files for HSDC Pro are
not
included with the HSDC Pro version 4.2 available on the TI
web at this time because the ADC is not a released device.
The ini files will have to be manually
copied into the ADC Files folder for the TSW14J56.
Please note that the configuration files for setting up the LMK04828 clocking device are different for the
DDC case than they are for the non-decimation (5-sample) case. The different modes of operation of the
ADC will affect the data rate on the JESD204B interface and thus affect the clocking needed for the
FPGA. The configuration files are
not
interchangeable. For example, the
LMK_ADC32RF45_lmfs82820_2457p6_MSPS.cfg file and LMK_ADC32RF80_2457MSPS.cfg file will both
set the sample clock for the ADC at 2.4576 GHz, but the SYSREF and the device clock to the FPGA will
be different for the two files.
This document first introduces the software that must be installed on a PC, and then presents a basic
setup for the ADC32RF80 DDC case, followed by a setup for the ADC32RF45 5-sample mode, both
modes being clocked by an externally supplied clock, with the LMK04828 clock chip supplying SYSREF to
the ADC and clock/SYSREF to the TSW14J56. The last section covers what to do to supply an internally
generated sample clock to the ADC, by either the LMK04828 or LMX2582
This document focuses on what is needed to use the HSDC Pro version 4.2 available on the TI web. Later
revisions of HSDC Pro will likely contain all of the files needed to support the ADC32RF4x/RF80 so that
some of the manual steps of the following setup would no longer be necessary.
