4.2 Real Decimation Mode
The following software configuration steps will program the ADC366xEVM in 16x Real Decimation mode.
4.2.1 ADC35XX GUI: Real Decimation Mode Configuration (2W, 16bit)
This procedure applies specifically to the ADC3663EVM, but can be applied to other sampling rates and bit
resolutions. See
for examples for clock rates in Real Decimation mode.
Table 4-2. 16-bit, Real Decimation Sample rate and DCLKIN examples
Interface Mode
DCLKIN multiplier
Example Sample Clock
Real Decimation Factor
Required DCLKIN
Frequency
2 Wire
4
65 MSPS
2
130 MHz
1 Wire
8
32 MSPS
8
32 MHz
1/2 Wire
16
10 MSPS
32
5 MHz
For this 16x Real Decimation example, apply a 65 MHz signal to J9 (sample clock) and a 16.25 MHz signal to J7
(DCLKIN).
External ADC sampling clock source and DCLKIN source must be frequency locked. If this is not
performed, the captured data will appear scrambled. If using the onboard clocking option, the
sampling clock and DCLKIN are frequency locked.
Apply a 1 MHz signal to J2 (ensure bandpass filter is used to reduce harmonics and noise of signal generator).
After launching the ADC35xx GUI perform the following steps:
• Under Resolution, select 16 bit.
• Under DDC, Select Real.
• For Decimation Factor, select 16.
• To calculate the DCLKIN frequency, enter "65" in the Fs(MHz) field, and click calculate. This is informational
only.
• Ensure that "CDC Enable" is red (disabled).
• Click "Configure"
ADC GUI Configuration
SBAU366 – JANUARY 2021
ADC366xEVM Evaluation Module
13
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