Texas Instruments ADS5413EVM, User Manual

2-2

2.1

Schematic Diagram

The schematic diagram for the EVM is attached to the end of this document.

2.2

Circuit Function

The following paragraphs describe the function of individual circuits. See the
relevant data sheet for device operating characteristics.

2.2.1

Analog Inputs

The ADC has either transformer-coupled inputs or differential amplifier inputs
from a single-ended source. The inputs are provided via SMA connectors J1
and J2 on the EVM, which must be configured as follows:

1) For a 1:1 transformer coupled input to the ADC, a single-ended source is

connected to J2. R36, R38, SJP1 must be removed, and R41 and R45
must be installed. The input is ac coupled and has a 50-

Ω

 terminator. This

is the default configuration for the EVM.

2) For a differential amplifier input to the ADC, a single ended source is

connected to J1. R36, R38, and SJP1 must be installed, and R41 and R45
must be removed. The input has a 50-

Ω

 terminator.

2.2.2

Clock Inputs

The EVM provides separate inputs for the ADC clock and output buffer clock.
This allows the user to send a modified version of the ADC clock (inverted,
delayed, etc

…

) with the output data to generate the required setup and hold

times for the users interface.

2.2.2.1

True Differential ADC Clock

To provide a true differential clock, input a positive 65 MHz, 0-V offset, 0.5 V

p−p

amplitude sine-wave signal into J3 and the complimentary signal into J4. This
is the default configuration for the EVM

2.2.2.2

Single-Ended ADC Clock

To provide a single-ended ADC clock, simply connect a single-ended source
to J3. No board modifications are required.

2.2.2.3

Transformer-Coupled Differential ADC Clock

To provide a transformer-coupled differential clock using a single-ended input
source, configure the board as follows:

1) Install T2, R39, C31, and C32 and remove C25 and C40.

2) Connect the single-ended clock input to J12. The clock is ac-coupled and

terminated with 50 

Ω

.

2.2.2.4

Buffer Clock

To provide a clock to the output buffer, apply a +3.3 V, 1.65-V offset signal input
to J9. This input is terminated with a 50-

Ω

 resistor to ground. This signal must

be the same frequency and synchronized with the ADC clock