Connecting to FPGA Platforms
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4.1.3
Test Result With Onboard VCXO and Differential LVPECL Clock
For the same setup as explained in the previous section, when Clock Option 3 (
) was used, the
FFT was captured as shown in
. The test results with Clock Option 2 are better than with Clock
Option 3. That is why Option 2 (clock with crystal filter) is recommended over the differential LVPECL
output.
Figure 11. ADC Performance With Clock Through Onboard VCXO,
CDCE72010 Configured for Differential LVPECL Output
4.2
TSW1100
When the ADS62PXX is configured in CMOS output mode users can use TI's
capture board.
Several additional board configuration steps are required before using this option.
•
Remove resistor packs with the following reference designators: RN7, RN8, RN9, RN10, RN11, RN12,
RN13 and RN14.
•
Install TI's SN74AVC16244 buffer into U12 and U13.
•
If using the parallel interface mode (JP11=1-2), configure the ADC in CMOS output mode using the
silkscreen on JP14.
22
ADS62PXXEVM
SLAU237B – May 2008 – Revised July 2010
Copyright © 2008–2010, Texas Instruments Incorporated