1
2
3
4
5
6
A
B
C
D
6
5
4
3
2
1
D
C
B
A
ti
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Engineer:
Revision History
REV
ECN Number
Approved
DOCUMENT CONTROL #:
1
3
BlockDiagram.sch
A
DATE:
31-Jan-2009
ADS8471/ADS8472EVM Block Diagram
6485904
-IN
+IN
B
_
C
S
B
_
R
D
B
_
C
O
N
V
S
T
B
_
B
Y
T
E
B
_
B
U
S
1
8
/1
6
B
U
S
Y
D
B
[1
7
..
.0
]
EXT_REF
Analog-to-Digital Converter
B_DB[17...0]
D
B
[1
7
..
.0
]
C
S
R
D
C
O
N
V
S
T
B
Y
T
E
B
U
S
1
8
/1
6
B
_
B
U
S
Y
B
U
S
Y
B
_
C
S
B
_
R
D
B
_
C
O
N
V
S
T
B
_
B
Y
T
E
B
_
B
U
S
1
8
/1
6
+AVCC
+VA
-VA
+BVDD
IN
T
c
D
C
_
C
S
A
0
A
1
A
2
D
C
_
C
O
N
V
S
T
Power & Digital Buffer
B_DB[17...0]
D
B
[1
7
..
.0
]
+BVDD
TP3
TP6
TP5
TP4
CS
RD
CONVST
BYTE
BUS18/16
B_BUSY
ADC Control
1
2
3
4
5
6
7
8
9
11
10
12
J6
TP1
TP2
1
2
3
4
5
6
7
8
9
10
J5
+VA
-VA
+5VD
AGND
+5VA
DGND
+3.3VD
W1
Lijoy Philipose
Lijoy Philipose
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P3
Parallel Control
INTC
A1
DC_CS
A2
ADC Data Bus
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
P2
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
B_DB16
B_DB17
Analog Input
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19 20
P1
J1
J2
DC_CONVST
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J7
40-PIN Header
B_DB17
B_DB16
B_DB15
B_DB14
B_DB13
B_DB12
B_DB11
B_DB10
B_DB9
B_DB8
B_DB7
B_DB6
B_DB5
B_DB4
B_DB3
B_DB2
INTc
TSW1100 Connector