3.1
Input Signal Conditioning
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Analog Interface
Table 1. Analog Input Connector
Description
Signal Name
Connector.Pin#
Signal Name
Description
Inverting Input Channel
—
P1.1
P1.2
+
Non-inverting Input Channel
Reserved
N/A
P1.3
P1.4
N/A
Reserved
Reserved
N/A
P1.5
P1.6
N/A
Reserved
Reserved
N/A
P1.7
P1.8
N/A
Reserved
Reserved
N/A
P1.9
P1.10
N/A
Reserved
Pin tied to Ground
AGND
P1.11
P1.12
N/A
Reserved
Pin tied to Ground
AGND
P1.13
P1.14
N/A
Reserved
N/A
Reserved
P1.15
P1.16
N/A
Reserved
Pin tied to Ground
AGND
P1.17
P1.18
N/A
Reserved
Pin tied to Ground
AGND
P1.19
P1.20
REF+
External Reference Input
The analog input circuitry, consisting of the THS4031 and THS4032 operational amplifiers, allow the user
to install passive components to configure it for positive or negative gains, as well as input range scaling,
filtering and leveling translation (e.g., adding a DC offset). The operational amplifiers are housed in an
industry standard SOIC footprint. This enables the user to replace the THS4031 with a plethora of dual
and single supply amplifiers housed in an SOIC package.
When choosing the driver amplifier the user should consider the following requirements. The driving
amplifier must be able to settle the input to 16-bit level within the sample time of the converter. It should
have Total Harmonic Distortion(THD) characteristics comparable to or better than the ADS8472. Lastly,
the noise generated by the amplifier needs to be as low as possible, so as not to degrade the SNR
performance of the ADS8472.
The noise coming through the driver amplifiers are filtered by a single-pole filter using R = 10.2
Ω
and C=
2.2nF with a corner frequency of 7MHz. The 5.1-
Ω
series resistor works with the capacitor to filter the input
signal, but also isolates the amplifier from the capacitive load. The 2200-pF capacitor to ground at the
input of the ADC works with the series resistor to filter the input signal, behaves like a charge reservoir,
and provides a path to ground for high-frequency noise and the low small input current transient which
occurs when the device switches from hold to sample mode. This external filter capacitor works with the
amplifier to charge the internal sampling capacitor during sampling mode.
The supplies to the input amplifier are selectable with solder jumper pad SJP3, and SJP4. Shorting across
pads 1 and 2 will ground the negative rail. Shorting across pads 2 and 3 will tie the negative supply of the
amplifiers to the voltage applied at node –VCC.
When deciding on supply rails, a good rule of thumb is to add at least 2V of head room on either side to
achieve optimal performance. For example, if the signal applied to the amplifier is 0–4V, then the amplifier
rails should be at least –2V and +6V. At the 16-bit performance node, the amplifier introduced distortion
can become significant. Be aware when reading amplifiers data sheets that they may not be specified with
large amplitudes. Therefore, it may not be possible to surmise from a cursory glance how well the
amplifier will behave in system.
Single-ended signal sources are readily available, but rarely allow the user to evaluate the full
performance of 16-bit converters. Although the ADS8472EVM can be configured for this input
configuration, the factory set configuration of the input circuitry is for a bipolar fully differential input signal.
The necessary DC component to offset the signal at U7 is generated by U4. U4 is the low noise THS4032
amplifier. It can be configured to further filter the reference voltage IC, U2, and provide positive or negative
gains. The ADS8472EVM leaves the factory with potentiometer, R24, set to 2.048V and set as shown in
.
indicates how the solder pad jumpers should be set to select from the various supply
and input options for the analog driver circuitry. The copy of the schematic for the ADS8472EVM is
attached at the end of this document.
SLAU203 – February 2007
ADS8472EVM
3
