Texas Instruments ADS866 Series, Manual

Page 1: ... of Input Overvoltage Protection Up to 20 V 500 kSPS The devices feature integrated analog On Chip 4 096 V Reference with Low Drift front end circuitry for each input channel with Excellent Performance overvoltage protection up to 20 V a 4 or 8 channel multiplexer with automatic and manual scanning 500 kSPS Aggregate Throughput modes and an on chip 4 096 V reference with low DNL 0 2 LSB INL 0 2 LS...

Page 2: ... 5 12 Device and Documentation Support 71 7 3 Recommended Operating Conditions 5 12 1 Documentation Support 71 7 4 Thermal Information 5 12 2 Related Links 71 7 5 Electrical Characteristics 6 12 3 Community Resources 71 7 6 Timing Requirements Serial Interface 10 12 4 Trademarks 71 7 7 Typical Characteristics 11 12 5 Electrostatic Discharge Caution 71 8 Detailed Description 22 12 6 Glossary 71 8 1...

Page 3: ...l communication Active low logic input 2 RST PD Digital input Dual functionality to reset or power down the device 3 DAISY Digital input Chain the data input during serial communication in daisy chain mode Active low logic input to enable the internal reference When low the internal reference is enabled 4 REFSEL Digital input REFIO becomes an output that includes the VREF voltage When high the int...

Page 4: ...ut Analog input channel 3 negative input Decouple with AIN_3P on pin 23 23 AIN_3P Analog input Analog input channel 3 positive input Decouple with AIN_3GND on pin 22 Analog input channel 4 negative input Decouple with AIN_4P on pin 25 24 NC AIN_4GND Analog input No connection for the ADS8664 this pin can be left floating or connected to AGND Analog input channel 4 positive input Decouple with AIN_...

Page 5: ... AIN_nP AIN_nGND Human body model HBM per ANSI ESDA JEDEC JS 001 1 Electrostatic V ESD V discharge All other pins 2000 Charged device model CDM per JEDEC specification JESD22 C101 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control proces...

Page 6: ...EF A Input range 0 625 VREF 0 0 625 VREF A Input range 0 3125 VREF 0 0 3125 VREF A Operating input range AIN_nGND All input ranges 0 1 0 0 1 V B negative input At TA 25 C zi Input impedance 0 85 1 1 15 MΩ B all input ranges Input impedance drift All input ranges 7 25 ppm C B VIN 2 25 With voltage at AIN_nP pin VIN A input range 2 5 VREF RIN VIN 2 00 With voltage at AIN_nP pin VIN A input range 1 2...

Page 7: ...ture drift All input ranges 1 5 ppm C B At TA 25 C EO Offset error 1 2 5 mV A all input ranges Offset error matching At TA 25 C 1 2 5 mV A channel to channel all input ranges Input range 2 5 VREF 1 3 B Input range 1 25 VREF 1 3 B Input range 0 625 VREF 1 3 B Input range 0 3125 VREF 2 6 B Offset error temperature drift Input range 0 15625 VREF 4 12 ppm C B Input range 0 to 2 5 VREF 1 3 B Input rang...

Page 8: ...alk memory 8 90 dB B to 2 maximum input voltage BW 3 dB Small signal bandwidth 3 dB At TA 25 C all input ranges 15 kHz B BW 0 1 dB Small signal bandwidth 0 1 dB At TA 25 C all input ranges 2 5 kHz B AUXILIARY CHANNEL Resolution 12 Bits A V AUX_IN AUX_IN voltage range AUX_IN AUX_GND 0 VREF V A AUX_IN 0 VREF V A Operating input range AUX_GND 0 V A During sampling 75 pF C Ci Input capacitance During ...

Page 9: ...specified 2 7 3 3 5 25 B performance For the ADS8668 AVDD 5 V fS 13 16 A maximum and internal reference Dynamic IAVDD_DYN mA AVDD For the ADS8664 AVDD 5 V fS 8 5 11 5 A maximum and internal reference For the ADS8668 AVDD 5 V device not converting and internal 10 12 A reference IAVDD_STC Analog supply current Static mA For the ADS8664 AVDD 5 V device not converting and internal 5 5 8 5 A reference ...

Page 10: ...lock frequency fS max 17 MHz tSCLK Serial clock time period fS max 59 ns tCONV Conversion time 850 ns tDZ_CSDO Delay time CS falling to data enable 10 ns tD_CKCS Delay time last SCLK falling to CS rising 10 ns tDZ_CSDO Delay time CS rising to SDO going to 3 state 10 ns TIMING REQUIREMENTS tACQ Acquisition time 1150 ns tPH_CK Clock high time 0 4 0 6 tSCLK tPL_CK Clock low time 0 4 0 6 tSCLK tPH_CS ...

Page 11: ... 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF 15 9 3 3 9 15 10 6 2 2 6 10 Analog Input Current µA Input Voltage V C002 400C 250C 1250C ADS8664 ADS8668 www ti com SBAS492 JULY 2015 7 7 Typical Characteristics At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Input range 2 5 VREF Figure 2 Input I V Characteristic Figure 3 Input Current vs Temperature...

Page 12: ...V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Mean 2048 sigma 0 1 input 0 V Mean 2048 sigma 0 0 input 1 25 VREF range 0 625 VREF range 2 5 VREF Figure 8 DC Histogram for Mid Scale Inputs 0 625 VREF Figure 9 DC Histogram for Mid Scale Inputs 2 5 VREF Mean 2048 sigma 0 0 input 0 625 VREF Mean 2048 sigma 0 1 input 0 V range 1 25 VREF range 0 3125 VREF Figure 10 DC Hist...

Page 13: ...3072 3584 4096 Differential Nonlinearity LSB Codes LSB C016 ADS8664 ADS8668 www ti com SBAS492 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted All input ranges Mean 2048 sigma 0 18 input 0 15625 VREF range 0 3125 VREF Figure 14 DC Histogram for Mid Scale Inputs Figure 15 Typical DNL for All Codes 0...

Page 14: ...8 3072 4096 Integral Nonlinearity LSB Codes LSB C022 ADS8664 ADS8668 SBAS492 JULY 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Range 1 25 VREF Figure 20 Typical INL for All Codes Figure 21 Typical INL for All Codes Range 0 3125 VREF Range 0 15625 VREF Figure 22 Typical INL f...

Page 15: ...m Maximum 0 5 0 3 0 1 0 1 0 3 0 5 40 7 26 59 92 125 Integral Nonlinearity LSB Free Air Temperature oC C028 Maximum Minimum ADS8664 ADS8668 www ti com SBAS492 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Range 1 25 VREF Figure 26 INL vs Temperature 2 5 VREF Figure 27 INL vs Tempera...

Page 16: ...ee Air Temperature oC C033 Minimum Maximum 0 5 0 3 0 1 0 1 0 3 0 5 40 7 26 59 92 125 Integral Nonlinearity LSB Free Air Temperature oC C034 Maximum Minimum ADS8664 ADS8668 SBAS492 JULY 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 0 15625 VREF Range 0 625 VREF Figure 32 INL vs Tempera...

Page 17: ...00 250 300 0 0 5 1 1 5 2 2 5 3 3 5 4 Number of Units Gain Drift ppm oC C040 ADS8664 ADS8668 www ti com SBAS492 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Figure 38 Gain Error vs Temperature Across Input Ranges Figure 39 Typical Histogram for Gain Error Drift Range 2 5 VREF Figur...

Page 18: ... fSAMPLE 500 kSPS unless otherwise noted Number of points 4k fIN 1 kHz SNR 73 65 dB Number of points 4k fIN 1 kHz SNR 73 67 dB SINAD 73 64 dB THD 92 382 dB SFDR 94 dB SINAD 73 67 dB THD 93 93 dB SFDR 94 dB Figure 44 Typical FFT Plot 0 625 VREF Figure 45 Typical FFT Plot 2 5 VREF Number of points 4k fIN 1 kHz SNR 73 64 dB Number of points 4k fIN 1 kHz SNR 73 44 dB SINAD 73 64 dB THD 91 022 dB SFDR ...

Page 19: ...6 VREF 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF 160 120 80 40 0 0 50000 100000 150000 200000 250000 Amplitude dB Input Frequency Hz C051 70 71 72 73 74 75 100 1000 10000 Signal to Noise Ratio dB Input Frequency Hz C052 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF 0 156 VREF 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF ADS8664 ADS8668 www ti com SBAS492 JULY 2015 Typical Characteristics continued At TA ...

Page 20: ...lk dB Input Frequency Hz C058 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF 0 156 VREF 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF 120 110 100 90 80 40 7 26 59 92 125 Total Harmonic Distortion dB Free Air Temperature oC C057 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF 0 156 VREF 2 5 VREF 1 25 VREF 0 625 VREF 0 3125 VREF ADS8664 ADS8668 SBAS492 JULY 2015 www ti com Typical Characteristics continued At TA 2...

Page 21: ...ture oC C078 ADS8664 ADS8668 www ti com SBAS492 JULY 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Figure 63 AVDD Current vs Temperature for the ADS8664 Figure 62 AVDD Current vs Temperature for the ADS8668 fS 500 kSPS During Sampling Figure 64 AVDD Current vs Temperature for the ADS8664 Figure 65 AVD...

Page 22: ...mable gain amplifier PGA and a second order antialiasing filter that conditions the input signal before being fed into a 4 or 8 channel analog multiplexer MUX The output of the MUX is digitized using a 12 bit analog to digital converter ADC based on the successive approximation register SAR architecture This overall system can achieve a maximum throughput of 500 kSPS combined across all channels T...

Page 23: ...nput channel and the AIN_nGND pin The devices allow a 0 1 V range on the AIN_nGND pin for all analog input channels This feature is useful in modular systems where the sensor or signal conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible In such cases running separate wires fro...

Page 24: ...ltage AVDD 5 V or offers a low impedance of 30 kΩ the internal overvoltage protection circuit can withstand up to 20 V on the analog input pins Table 1 Input Overvoltage Protection Limits When AVDD 5 V or Offers a Low Impedance of 30 kΩ 1 INPUT CONDITION TEST ADC COMMENTS VOVP 20 V CONDITION OUTPUT All input VIN VRANGE Within operating range Valid Device functions as per data sheet specifications ...

Page 25: ... in Table 2 Table 2 Input Overvoltage Protection Limits When AVDD Floating with Impedance 30 kΩ 1 INPUT CONDITION TEST ADC OUTPUT COMMENTS VOVP 11 V CONDITION Device is not functional but is protected internally by VIN VOVP Within overvoltage range All input ranges Invalid the OVP circuit This usage condition may cause irreversible damage VIN VOVP Beyond overvoltage range All input ranges Invalid ...

Page 26: ...nt analog input voltage ranges The PGA uses a very highly matched network of resistors for multiple gain configurations Matching between these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low across all channels and input ranges Table 3 Input Range Selection Bits Configuration Range_CHn 3 0 ANALOG INPUT RANGE BIT 3 BIT 2 BIT 1 BIT 0 2 5 VREF...

Page 27: ... the Channel Sequencing Modes section In manual mode MAN_Ch_n the channel is selected for every sample via a register write in auto scan mode AUTO_RST the channel number is incremented automatically on every CS falling edge after the present channel is sampled The analog inputs can be selected for an auto scan with register settings see the Auto Scan Sequencing Control Registers section The device...

Page 28: ...e internal band gap circuit creates a low pass filter with this capacitor to band limit the noise of the reference The use of a smaller capacitor value allows higher reference noise in the system thus degrading SNR and SINAD performance Do not use the REFIO pin to drive external ac or dc loads because REFIO has limited current output capability The REFIO pin can be used as a source if followed by ...

Page 29: ...n in Figure 75 Although all tested units exhibit a positive shift in their output voltages negative shifts are also possible Note that the histogram in Figure 75 shows the typical shift for exposure to a single reflow profile Exposure to multiple reflows which is common on PCBs with surface mount components on both sides causes additional shifts in the output voltage If the PCB is to be exposed to...

Page 30: ...this mode because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin which is internally connected to the ADC reference input The output of the external reference must be appropriately filtered to minimize the resulting effect of the reference noise on system performance A typical connection diagram for this mode is shown in Figure 78 Figure 78 Device Connect...

Page 31: ...rovides direct interface to an internal high precision 12 bit ADC through the multiplexer because this channel does not include the front end analog signal conditioning that the other analog input channels have The AUX channel supports a single unipolar input range of 0 V to VREF because there is no front end PGA The input signal on the AUX_IN pin can vary from 0 V to VREF whereas the AUX_GND pin ...

Page 32: ...ain Error Offset Error ADS8664 ADS8668 SBAS492 JULY 2015 www ti com The AUX channel in the ADS8664 and ADS8668 offers a true 12 bit performance with no missing codes Some typical performance characteristics of the AUX channel are shown in Figure 81 to Figure 84 AUX channel Mean 2048 sigma 0 Figure 82 Offset and Gain vs Temperature Figure 81 DC Histogram for Mid Scale Input AUX Channel AUX Channel ...

Page 33: ...inimizes the harmonic distortion at higher input frequencies In general the amplifier bandwidth requirements can be calculated on the basis of Equation 1 where f 3dB is the 3 dB bandwidth of the RC filter 1 Distortion In order to achieve the distortion performance of the AUX channel the distortion of the input driver must be at least 10 dB lower than the specified distortion of the internal ADC as...

Page 34: ...ative full scale NFS input voltage The LSB size is equal to FSR 212 FSR 4096 because the resolution of the ADC is 12 bits For a reference voltage of VREF 4 096 V the LSB values corresponding to the different input ranges are listed in Table 4 Figure 85 12 Bit ADC Transfer Function Straight Binary Format Table 4 ADC LSB Values for Different Input Ranges VREF 4 096 V INPUT RANGE POSITIVE FULL SCALE ...

Page 35: ... high alarm threshold T hysteresis H The alarm resets when the digital output for the channel is less than or equal to the high alarm lower limit high alarm T H 2 This function is shown in Figure 86 Similarly the lower alarm is triggered when the digital output for a particular channel falls below the low alarm lower limit low alarm threshold T H 1 The alarm resets when the digital output for the ...

Page 36: ...t for the data interface All synchronous accesses to the device are timed with respect to the falling edges of the SCLK signal 8 4 1 1 3 SDI Input SDI is the serial data input line SDI is used by the host processor to program the internal device registers for device configuration At the beginning of each data frame the CS signal goes low and the data on the SDI line are read by the device at every...

Page 37: ... PWR_DN mode and the program registers are reset to default tPL_RST_PD 400 ns value The devices can be placed into power down PWR_DN mode by pulling the RST PD pin to a logic low state for at least 400 ns The RST PD pin is asynchronous to the clock thus RST PD can be triggered at any time regardless of the status of other pins including the analog input channels When the device is in power down mo...

Page 38: ...il the 16th falling edge appears on the SCLK input Because the ADC conversion time is fixed the maximum value is given in the Electrical Characteristics table the 16th SCLK falling edge must appear after the internal conversion is over otherwise data output from the device is incorrect Therefore the SCLK frequency cannot exceed a maximum value as provided in the Timing Requirements Serial Interfac...

Page 39: ...vices sample the input signal at their respective selected channels and enter into conversion phase For the first 16 SCLK cycles the internal register settings for the next conversion can be entered using the SDI line that is common to all devices in the chain During this time period the SDO outputs for all devices remain low At the end of conversion every ADC in the chain loads its own conversion...

Page 40: ...trolled by separate CS control lines from the host controller Figure 94 Star Topology Connection Schematic The timing diagram for a typical data frame in the star topology is the same as in a stand alone device operation as illustrated in Figure 91 The data frame for a particular device starts with the falling edge of the CS signal and ends when the CS signal goes high Because the host controller ...

Page 41: ...erent modes of the device After power up the program registers wake up with the default values and require appropriate configuration settings before performing any conversion The diagram in Figure 95 explains how to switch the device from one mode of operation to another Figure 95 State Transition Diagram 8 4 2 1 Continued Operation in the Selected Mode NO_OP Holding the SDI line low continuously ...

Page 42: ...l on the previously selected channel 8 4 2 3 STANDBY Mode STDBY The devices support a low power standby mode STDBY in which only part of the circuit is powered down The internal reference and buffer is not powered down and therefore the devices can be quickly powered up in 20 µs on exiting the STDBY mode When the device comes out of STDBY mode the program registers are not reset to the default val...

Page 43: ... CS falling edge the device samples the analog input at the channel selected by the MAN_CH_n command or the first channel of the AUTO_RST mode sequence To ensure that the input signal is sampled correctly keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device internal circuitry can be fully powered up and biased properly before taking the sample The data output for...

Page 44: ... power down To enter PWR_DN mode using software execute a valid write operation on the command register with a software PWR_DN command of 8300h as shown in Figure 98 The command is executed and the device enters PWR_DN mode on the next CS rising edge following this write operation The device remains in PWR_DN mode if no valid conversion command AUTO_RST or MAN_Ch_n is executed and SDI remains low ...

Page 45: ...te frame of 32 SCLK cycles The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control register 01h to 02h in the program register see the Program Register Map section In this mode the devices continuously cycle through the selected channels in ascending order beginning with the lowest channel and converting all channels selected in the program register On...

Page 46: ...n be pulled high immediately after the MAN_Ch_n command or after reading the output data of the frame However in order to accurately acquire and convert the input signal on the next channel the command frame must be a complete frame of 32 SCLK cycles See Table 6 for a list of commands to select individual channels during MAN_Ch_n mode Figure 102 Enter MAN_Ch_n Scan Mode Timing Diagram The manual c...

Page 47: ...automatic scan using the AUTO_RST command When the reset command is received the ongoing auto mode sequence is reset and restarts from the lowest selected channel in the sequence In MAN_Ch_n mode the same input channel is selected during every data conversion frame The input command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6 If a particular input channel is s...

Page 48: ... shown in Figure 106 The device remains in RST mode if no valid conversion command AUTO_RST or MAN_Ch_n is executed and SDI remains low see the Continued Operation in the Selected Mode NO_OP section during the subsequent data frames When the device operates in RST mode the program register settings can be updated as explained in the Program Register Read Write Operation section using 16 SCLK cycle...

Page 49: ...a frame when the CS signal goes high Table 6 Command Register Map MSB BYTE LSB BYTE COMMAND REGISTER OPERATION IN NEXT FRAME Hex B15 B14 B13 B12 B11 B10 B9 B8 B 7 0 Continued Operation 0 0 0 0 0 0 0 0 0000 0000 0000h Continue operation in previous mode NO_OP Standby 1 0 0 0 0 0 1 0 0000 0000 8200h Device is placed into standby mode STDBY Power Down 1 0 0 0 0 0 1 1 0000 0000 8300h Device is powered...

Page 50: ... Read Write Operation The program register is a 16 bit read or write register There must be a minimum of 24 SCLKs after the CS falling edge for any read or write operation to the program registers When CS goes low the SDO line goes low as well The device receives the command see Table 7 and Table 8 through SDI where the first seven bits bits 15 9 represent the register address and the eighth bit b...

Page 51: ...he 8 bit data from the addressed register during the next eight clocks in MSB first fashion A typical timing diagram for a program register read cycle is shown in Figure 108 Table 8 Read Cycle Command Word REGISTER ADDRESS WR RD DATA PIN Bits 15 9 Bit 8 Bits 7 0 SDI ADDR 6 0 0 XXXXX SDO 0000 000 0 DOUT 7 0 Figure 108 Program Register Read Cycle Timing Diagram Copyright 2015 Texas Instruments Incor...

Page 52: ...Flag Ch2 Flag Ch1 Flag Ch0 Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm ALARM Ch 0 3 Tripped Flag 11h 00h Flag Ch0 Low Flag Ch0 High Flag Ch1 Low Flag Ch1 High Flag Ch2 Low Flag Ch2 High Flag Ch3 Low Flag Ch3 High Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm ALARM Ch 0 3 Ac...

Page 53: ...H0_LT 11 4 Ch 0 Low Threshold LSB 19h 00h CH0_LT 3 0 0 0 0 0 See the Alarm Threshold Setting Registers for details regarding the ALARM threshold settings registers Ch 7 Hysteresis 38h 00h CH7_HYST 3 0 0 0 0 0 Ch 7 High Threshold MSB 39h FFh CH7_HT 11 4 Ch 7 High Threshold LSB 3Ah F0h CH7_HT 3 0 0 0 0 0 Ch 7 Low Threshold MSB 3Bh 00h CH7_LT 11 4 Ch 7 Low Threshold LSB 3Ch 00h CH7_LT 3 0 0 0 0 0 COM...

Page 54: ...or A read operation on any of these bits or registers outputs all 1 s on the SDO line Table 10 AUTO_SEQ_EN Field Descriptions Bit Field Type Reset Description 7 CH7_EN R W 1h Channel 7 enable 0 Channel 7 is not selected for sequencing in AUTO_RST mode 1 Channel 7 is selected for sequencing in AUTO_RST mode 6 CH6_EN R W 1h Channel 6 enable 0 Channel 6 is not selected for sequencing in AUTO_RST mode...

Page 55: ...6 can be included in the AUTO_RST sequence 1 The analog front end on channel 6 is powered down and channel 6 cannot be included in the AUTO_RST sequence 5 CH5_PD R W 0h Channel 5 power down 0 The analog front end on channel 5 is powered up and channel 5 can be included in the AUTO_RST sequence 1 The analog front end on channel 5 is powered down and channel 5 cannot be included in the AUTO_RST sequ...

Page 56: ... 2 0 16th SCLK falling edge Conversion result for selected 000 SDO pulled low no latency channel MSB first 16th SCLK falling edge Conversion result for selected Channel 001 SDO pulled low no latency channel MSB first address 1 16th SCLK falling edge Conversion result for selected Channel Device SDO pulled 010 no latency channel MSB first address 1 address 1 low 16th SCLK falling edge Conversion re...

Page 57: ...0 0 Range_CHn 3 0 R 0h R 0h R 0h R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 15 Channel n Input Range Registers Field Descriptions Bit Field Type Reset Description 7 4 0 R 0h Must always be set to 0 3 0 Range_CHn 3 0 R W 0h Input range selection bits for channel n n 0 to 3 for the ADS8664 and n 0 to 7 for the ADS8668 0000 Input range is set to 2 5 x VREF 0001 Input rang...

Page 58: ...larm Tripped Alarm Tripped Alarm Flag Ch7 1 Flag Ch6 Flag Ch5 Flag Ch4 Flag Ch3 Flag Ch2 Flag Ch1 Flag Ch0 R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R Read only n value after reset 1 Shading indicates bits or registers that are not included in the 4 channel version of the device A write operation on any of these bits or registers has no effect on device behavior A read operation on any of the...

Page 59: ...rm Active Alarm Active Alarm Active Alarm Flag Ch0 Low Flag Ch0 High Flag Ch1 Low Flag Ch1 High Flag Ch2 Low Flag Ch2 High Flag Ch3 Low Flag Ch3 High R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R Read only n value after reset Table 18 ALARM Ch0 3 Active Flag Register Field Descriptions Bit Field Type Reset Description 7 0 Active Alarm Flag Ch n Low R 0h Active alarm flag high low for channel n ...

Page 60: ...channel version of the device A write operation on this register has no effect on device behavior A read operation on this register outputs all 1 s on the SDO line Table 20 ALARM Ch4 7 Active Flag Register Field Descriptions Bit Field Type Reset Description 7 0 Active Alarm Flag Ch n Low R 0h Active alarm flag high low for channel n n 4 to 7 or High n 4 to 7 Each individual bit indicates an active...

Page 61: ...CH2_LT 3 0 0 0 0 0 Ch 3 Hysteresis 24h CH3_HYST 3 0 0 0 0 0 Ch 3 High Threshold MSB 25h CH3_HT 11 4 Ch 3 High Threshold LSB 26h CH3_HT 3 0 0 0 0 0 Ch 3 Low Threshold MSB 27h CH3_LT 11 4 Ch 3 Low Threshold LSB 28h CH3_LT 3 0 0 0 0 0 Ch 4 Hysteresis 1 29h CH4_HYST 3 0 0 0 0 0 Ch 4 High Threshold MSB 2Ah CH4_HT 11 4 Ch 4 High Threshold LSB 2Bh CH4_HT 3 0 0 0 0 0 Ch 4 Low Threshold MSB 2Ch CH4_LT 11 4...

Page 62: ... 0 to 7 for the ADS8668 n 0 to 3 for the ADS8664 Figure 119 Ch n High Threshold MSB Registers 7 6 5 4 3 2 1 0 CHn_HT 11 4 R W 1h LEGEND R W Read Write n value after reset Table 22 Channel n High Threshold MSB Register Field Descriptions n 0 to 7 for the ADS8668 n 0 to 3 for the ADS8664 Bit Field Type Reset Description 7 0 CHn_HT 15 8 R W 1h These bits set the MSB byte for the 12 bit channel n high...

Page 63: ... is Fh 3 0 CHn_HT 3 0 R 0h Read only bit internally set to 0 n 0 to 7 for the ADS8668 n 0 to 3 for the ADS8664 Figure 121 Ch n Low Threshold MSB Registers 7 6 5 4 3 2 1 0 CHn_LT 11 4 R W 0h LEGEND R W Read Write n value after reset Table 24 Channel n Low Threshold MSB Register Field Descriptions n 0 to 7 for the ADS8668 n 0 to 3 for the ADS8664 Bit Field Type Reset Description 7 0 CHn_LT 15 8 R W ...

Page 64: ...B is 2h to Eh 1111 LSB is Fh 3 0 CHn_LT 3 0 R 0h Read only bit internally set to 0 n 0 to 7 for the ADS8668 n 0 to 3 for the ADS8664 8 5 2 3 6 Command Read Back Register address 3Fh This register allows the device mode of operation to be read On execution of this command the device outputs the command word executed in the previous data frame The output of the command register appears on SDO from t...

Page 65: ... include an integrated analog front end for each input channel and an integrated precision reference with a buffer As such this device family does not require any additional external circuits for driving the reference or analog input pins of the ADC 9 2 Typical Applications 9 2 1 Phase Compensated 8 Channel Multiplexed Data Acquisition System for Power Automation Figure 124 8 Channel Multiplexed D...

Page 66: ...mum latency in data output resulting from the SAR architecture The integration offered by this device makes the ADS8664 and ADS8668 an ideal selection for such applications because the integrated signal conditioning helps minimize system components and avoids the need for generating high voltage supply rails The overall system level dc precision gain and offset errors and low temperature drift off...

Page 67: ...are given below Up to eight channels of user programmable inputs Voltage inputs with a typical ZIN of 1 MΩ 10 V 5 V 2 5 V 0 V to 10 V and 0 V to 5 V Current inputs with a ZIN of 300 Ω 0 mA to 20 mA 4 mA to 20 mA and 20 mA A 12 bit SAR ADC with SPI Accuracy of 0 2 at 25 C over the entire input range of voltage and current inputs Onboard isolated Fly Buck power supply with inrush current protection ...

Page 68: ...nsient voltage suppressor TVS and ESD diodes The RC low pass mode filters are used on each analog input before the input reaches the ADS8668 thus eliminating any high frequency noise pickups and minimizing aliasing For a step by step design procedure circuit schematics bill of materials PCB files simulation results and test results see 16 Bit 8 Channel Integrated Analog Input Module for Programmab...

Page 69: ...the bypass capacitors must be avoided All ground pins must be connected to the ground plane using short low impedance paths There are two decoupling capacitors used for the REFCAP pin The first is a small 1 μF X7R grade 0603 size ceramic capacitor placed close to the device pins for decoupling the high frequency signals and the second is a 22 µF X7R grade 1210 size ceramic capacitor to provide the...

Page 70: ...D 25 AIN_4P 24 AIN_4GND 23 AIN_3P 22 AIN_3GND 21 AIN_2P 20 AIN_2GND 1µF 22µF GND GND GND GND GND 10µF GND 1µF GND CS SCLK SDO SDI RST PD REFSEL DAISY Optional RC Filter for Channel AIN_0 to AIN_7 1µF Digital Pins Analog Pins 10µF When using internal VREF ADS8664 ADS8668 SBAS492 JULY 2015 www ti com 11 2 Layout Example Figure 128 Board Layout for the ADS8664 and ADS8668 70 Submit Documentation Feed...

Page 71: ...specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Online Community TI s Engineer to Engineer E2E Community Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers Design Support TI s Design Support Quickly find helpful E2E forums along with design support tool...

Page 72: ...nformation This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation 72 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links ADS8664 ADS8668 ...

Page 73: ...le for use in specified lead free processes TI may reference these types of products as Pb Free RoHS Exempt TI defines RoHS Exempt to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption Green TI defines Green to mean the content of Chlorine Cl and Bromine Br based flame retardants meet JS709B low halogen requirements of 1000ppm threshold Antimony...

Page 74: ...ing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis ...

Page 75: ...s SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant ADS8664IDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 ADS8668IDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 22 Jul 2015 Pack Materials Page 1 ...

Page 76: ...Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS8664IDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 ADS8668IDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 PACKAGE MATERIALS INFORMATION www ti com 22 Jul 2015 Pack Materials Page 2 ...

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