25
Histogram Analysis
.........................................................................................................
26
FFT Analysis
................................................................................................................
27
Phase Compensation Analysis
...........................................................................................
28
Simulation Mode
............................................................................................................
29
ADS8688EVM PCB: Top Layer (L1)
.....................................................................................
30
ADS8688EVM PCB: Ground Layer (L2)
................................................................................
31
ADS8688EVM PCB: Analog Power Layer (L3)
........................................................................
32
ADS8688EVM PCB: Digital Power Layer (L4)
.........................................................................
33
ADS8688EVM PCB: Ground Layer (L5)
................................................................................
34
ADS8688EVM PCB: Bottom Layer (L6)
.................................................................................
List of Tables
1
Related Documentation
.....................................................................................................
2
J7: Analog Interface Connections
.........................................................................................
3
Connecting Negative Analog Inputs to Ground
..........................................................................
4
Using Onboard, Second-Order, Butterworth, Low-Pass Filters
........................................................
5
Bypassing the Onboard, Second-Order, Butterworth, Low-Pass Filters
..............................................
6
Selecting the Reference for the ADS8688EVM
..........................................................................
7
External Reference Connections
..........................................................................................
8
Connector J19 Pin Out
......................................................................................................
9
Jumper Settings for Generating HVDD and HVSS Using an Onboard Switching Regulator
......................
10
Jumper Settings for Generating HVDD and HVSS from External High-Voltage Supplies
.........................
11
Power-Supply Connections
.................................................................................................
12
Default Jumper Configuration
.............................................................................................
13
ADS8688EVM Bill of Materials
..........................................................................................
3
SBAU230A – August 2014 – Revised December 2014
ADS8688EVM-PDK Evaluation Module
Copyright © 2014, Texas Instruments Incorporated