Texas Instruments AMIC110 ICE, User Manual

Page 1: ...LEDs 11 2 6 JTAG Emulation Circuit 13 2 7 Memory Interfaces 14 3 AMIC110 ICE Physical Specifications 18 3 1 Board Layout 18 3 2 Connector Index 19 4 Power Supply 22 4 1 Power Distribution 23 4 2 Sitara AMIC110 Current Consumption 23 4 3 Additional Components Current Consumption 23 4 4 Overall System Current Consumption 24 4 5 TPS650250 Power Dissipation 24 4 6 Measured Power Consumption of System ...

Page 2: ...n PWM modules eHRPWMs Three external DMA event inputs that can be used as interrupt inputs Three MMC SD and SDIO ports Two USB 2 0 high speed OTG ports with integrated PHY 324 pin S PBGA N324 package with 0 80 mm ball pitch The AMIC110 ICE has the following key features AMIC110 is based on the Sitara ARM Cortex A8 32 bit RISC processor at 300 MHz 512MB of DDR3 8MB of SPI Flash 32KB of I2 C EEPROM ...

Page 3: ...requirements Jack with external magnetics Copyright 2017 Texas Instruments Incorporated 3V3 PROFIBUS www ti com Introduction 3 SPRUIE6 April 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE 1 2 Functional Block Diagram Figure 1 shows the functional block diagram of the AMIC110 ICE device Figure 1 AMIC110 ICE Funct...

Page 4: ... a triangle is connected to pin 1 of J3 indicated by a dot on the silk screen See TTL to USB Serial Converter Range of Cables Datasheet for information about the TTL 232R 3V3 cable 4 Connect the USB connector of the serial cable to a PC host port 5 Connect a CAT5 Ethernet cable from a PC running TwinCAT software to PHY1 J6 ECAT IN of the ICE board If users have multiple ICE boards in a chain conne...

Page 5: ...fore the DC plug may damage the board To remove power from the AMIC110 ICE disconnect the AC plug of the power supply from the AC power source Then disconnect the DC plug of the power supply from the AMIC110 ICE 2 Interface Details 2 1 Boot Configuration Various boot configurations can be set by using pullup and pulldown resistor combinations on the SYSBOOT inputs LCD_DATA 15 0 pins Boot configura...

Page 6: ...rnal pull down along with an external pull down ensures the switch is off as soon as power is applied The SYSBOOT buffers U8 and U9 have an active low enable controlled by the MII1_RXD2 pin operating as GPIO2_19 which defaults to a high z input with an internal pull down after power is applied The internal pull down along with an external pull down ensures the buffer is enabled as soon as power is...

Page 7: ...on Feedback Copyright 2017 Texas Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE 2 2 Clock Distribution Figure 5 shows the clock distribution circuit Three 25 MHz crystals are used onboard One 25 MHz crystal is connected to the AMIC110 the second crystal is connected to PHY1 and the third crystal is connected to PHY2 Figure 5 Clock Distribution 2 3 Reset Circuit Distr...

Page 8: ...ort numerous industrial protocols The PRU subsystem supports two IEEE 802 3 Standard Media Independent Interface MII interfaces which can be connected to 10 100 Ethernet PHYs The AMIC110 ICE includes two DP83822 10 100 Ethernet PHYs which provide two Ethernet connections see Figure 7 The PHYs are implemented to support dual EtherCAT slave ports Figure 7 Ethernet Interface Without Bootstrap Hardwar...

Page 9: ...on default state for LCD_DATA 15 0 pins except LCD_DATA6 and LCD_DATA7 LCD_DATA6 and LCD_DATA7 should have their internal pulldown resistors turned on this holds the LCD_DATA6 and LCD_DATA7 pins in a valid logic state once the SYSBOOT buffers are turned off The GPMC_AD9 and LCD_PCLK pins should be in their power on default configuration operating in their respective GPIO mode with internal pullown...

Page 10: ...trapping Resistors Table 2 lists the configurations for PHY1 See the hardware bootstrap configurations section of DP83822 Robust Low Power 10 100 Mbps Ethernet Physical Layer Transceiver for more information Table 2 Ethernet PHY1 Strap Configuration Strap Setting Pin Name Strap Function Value of Strap Function Description Address COL PHY_AD0 1 1 RX_D0 PHY_AD1 0 RX_D1 PHY_AD2 0 RX_D3 PHY_AD3 0 Mode...

Page 11: ... Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE Figure 9 shows the industrial Ethernet PHY2 strapping resistors As shown in Figure 9 PHY2 has an address of 13 All other PHY2 bootstrap settings are the same as PHY1 Figure 9 Industrial Ethernet PHY2 Strapping Resistors 2 5 Ethernet Protocol Specific Indicator LEDs The AMIC110 ICE was built with a focus on EtherCAT The ...

Page 12: ...r port Green per port Green per port Behavior Solid on link blink on activity Solid on link blink on activity Solid on link blink on activity optional Solid on link Solid on link blink on command from PLC not on activity Activity LED Color Orange per port Orange per port Behavior Blink on activity Blink on activity Status and error LED Color Bicolor green and red Behavior RUN LED Color Green ERROR...

Page 13: ...ust be combined with a lens or changed to a multicolor LED to comply with standards such as SERCOS III Ethernet IP and Powerlink The parallel resistors R188 R189 R235 and R236 are required for the boot time configuration of the PHY Figure 10 AMIC110 ICE Indicator LEDs 2 6 JTAG Emulation Circuit The AMIC110 ICE supports a compact TI 20 pin connector in the design An external emulator and debugger p...

Page 14: ...E6 April 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE 2 7 Memory Interfaces 2 7 1 DDR3 Interface The AMIC110 ICE supports one 4 Gb 256Mx16 DDR3 chip MT41K256M16TW 107 from Micron to obtain a memory size of 512MB Figure 11 shows the DDR3 circuit NOTE No DDR or other external RAM is required when the EtherCAT sl...

Page 15: ...ues Parameters DDR3 clock frequency 400 MHz Invert Clkout 0 Trace length inches Byte 0 Byte 1 CK trace 0 94463 0 94463 DQS trace 0 915736 0 797452 Seed values per byte lane WR DQS 0 2 RD DQS 34 34 RD DQS GATE 67 62 Seed values to input to program WR DQS 0 RD DQS 1A RD DQS GATE 32 The following code snippet shows the optimum values obtained after running the DDR3_slave_ratio_search_auto out file in...

Page 16: ...I Flash The AMIC110 ICE includes an 8 MB serial Flash W25Q64FV from Winbond that is interfaced to the AMIC110 see Figure 12 The SPI port of the ICE is shared with the SPI Flash and the LaunchPad that is selected through chip select SPI0_CS0 and SPI1_CS0 The hold function to pause the serial communication without deselecting the device is disabled with a pullup resistor attached to the HOLD pin Pul...

Page 17: ...ammed with identification information for each board The remaining 32696 bytes are available to the user for data or code storage NOTE The first 72 bytes of addressable EEPROM memory should never be overwritten Table 5 lists the ID memory header information Table 5 ID Memory Header Information Name Size Bytes Contents Description Header 4 MSB 0xEE3355AA LSB Start code Board name 8 ICE110 Board nam...

Page 18: ...orporated AMIC110 Industrial Communications Engine AMIC110 ICE 3 AMIC110 ICE Physical Specifications 3 1 Board Layout The ICE board has dimensions of 2 204 inches 3 464 inches 56 mm 88 mm and is an 8 layer board fabricated with epoxy fiberglass FR4 grade material Figure 13 shows the top view of the AMIC110 ICE Figure 13 AMIC110 ICE Top ...

Page 19: ...rd Figure 14 AMIC110 ICE Bottom 3 2 Connector Index The AMIC110 ICE has several connectors that provide access to various interfaces on the board Table 6 lists these connectors Table 6 AMIC110 ICE Connectors Connector Part Number Pins Function J1 FTR 110 51 S D 06 20 JTAG Header J2 DF40HC 4 0 60DS 0 4V 51 60 High Density Interface Connector J3 PEC06SAAN 6 UART Header J4 J5 SSW 110 23 F D 20 Launch...

Page 20: ...Emulation 0 14 Emulation 1 15 Emulation Reset 16 JTAG test data output 17 Emulation 2 18 Emulation 3 19 Emulation 4 20 Ground 3 2 2 UART Header Table 8 lists the UART header pinout information Table 8 UART Header Pinout Pin Number Description 1 Ground 2 NC 3 NC 4 UART receive 5 UART transmit 6 NC 3 2 3 High Density Interface Connector Table 9 lists the high density interface connector pinout infor...

Page 21: ...et LP 60 NC 3 2 4 LaunchPad Headers Table 10 lists the LaunchPad header pinout for J4 Table 10 J4 LaunchPad Header Pinout Pin Number Description Pin Number Description 1 Power supply 2 Power supply 3 NC 4 Ground 5 EtherCAT Clock synchronization for PHY1 6 Analog input 0 7 EtherCAT Clock synchronization for PHY2 8 Analog input 1 9 UART 1 Receive 10 NC 11 GPIO 12 NC 13 Clock for serial communication...

Page 22: ...o the AMIC ICE follow the instructions in Section 1 4 for plugging and unplugging the power supply The 5 V input is converted into the required supply voltages using a PMIC The TPS650250RHBR PMIC U7 provides the required voltages and currents for all power rails of the AMIC110 processor see Table 12 Table 12 TPS650250 Power Rail Split to AMIC110 Rail TPS650250 AMIC110 1 1 V DCDC1 VDD_CORE VDD_MPU ...

Page 23: ...35x Power Consumption Summary was used for the worst case estimates of the AMIC110 power requirements The power requirements from the 3D Chameleon Man example were used because that was the example with the highest power consumption Table 13 lists the current consumption requirements of the AMIC110 including DDR3 1 DDR3 interface using 1 5 V Table 13 Current Consumption Requirements of AMIC110 Inc...

Page 24: ...n the AMIC110 Sitara SoC data sheet The MII signals have a 25 MHz clock frequency There is approximately 1 67 mA of drive current per 3 3 V I O pin Approximately 50 pins are used in this design Table 14 lists the current consumption requirements of the external circuit and estimated I O switching losses Table 14 Current Consumption Requirement of External Circuit and I O Switching Losses Rail Flas...

Page 25: ...m Power Consumption Rail Current Consumption Power Consumption 1 1 V 349 mA 0 384 W 1 5 V 35 8 mA 0 054 W 1 8 W 26 23 mA 0 047 W 3 3 V 128 mA 0 422 W The power consumption was measured by removing the 0 Ω resistors attached to each power rail and measuring with a multimeter over the removed resistor See the AMIC110 ICE Schematic Files for resistor details A multimeter was connected at the 5 V inpu...

Page 26: ...s Engine AMIC110 ICE 4 7 Thermal Test A thermal image was taken of the board while running the EtherCAT slave see Figure 16 This image is used see if there are thermal hot spots on the design Figure 16 Thermal Image of AMIC110 ICE The power supply heats up to approximately 37 C shown in Figure 16 The hottest spot on the board is the AMIC110 device which has a temperature rise of 18 1 C 4 8 Power U...

Page 27: ...t 2017 Texas Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE 4 9 Power Up Behavior of Onboard Supply Rails Figure 18 shows the power up sequence with the reset signal and the 1v1 1v5 and 3v3 rails Figure 18 Power Up Sequence Reset and 1v1 1v5 and 3v3 Rails ...

Page 28: ...Engine AMIC110 ICE Figure 19 shows the power up sequence with the reset signal and 1v5 1v8_x and 3v3 rails Rails 1v8_1 and 1v8_2 were measured at the same time They are identical for both the power up and power down sequences Thus the 1v8 rails are denoted as 1v8_x in Figure 19 through Figure 21 Figure 19 Power Up Sequence Reset and 1v5 1v8_x and 3v3 Rails ...

Page 29: ... Texas Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE 4 10 Power Down Behavior of Onboard Supply Rails Figure 20 shows the power down sequence with the reset signal and the 1v1 1v8_x and 3v3 rails Figure 20 Power Down Sequence Reset and 1v1 1v8_x and 3v3 Rails ...

Page 30: ... Instruments Incorporated AMIC110 Industrial Communications Engine AMIC110 ICE Figure 21 shows the power down sequence with the reset signal and the 1v5 1v8_x and 3v3 rails Figure 21 Power Down Sequence Reset and 1v5 1v8_x and 3v3 Rails 5 Known Issues There are no known issues for the AMIC110 ICE ...

Page 31: ...onnect to LaunchPad boards The following instructions detail connecting the AMIC110 ICE to the F28069M LaunchPad 1 Insert the AMIC110 ICE headers J4 and J5 to the F28069M LaunchPad headers J1 J3 J2 and J4 See Figure 22 Figure 22 AMIC110 ICE and F28069M LaunchPad Connection 1 of 2 2 Press the boards together gently to avoid PCB warping issues see Figure 23 Figure 23 AMIC110 ICE and F28069M LaunchPa...

Page 32: ... LaunchPad Devices www ti com 32 SPRUIE6 April 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated Figure 24 shows the connected AMIC110 ICE and F28069M LaunchPad boards Figure 24 Connected Devices ...

Page 33: ...bmit Documentation Feedback Copyright 2017 Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Date Revision Description April 2017 Initial release ...

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