Press the
Assign Selected VCO Settings to Device
to update the VCO frequencies. Press the
Apply Output
Clock Settings to Device
button. By default, the analog PLL frequencies are shown; however the DPLL
calculated frequency from step 6 will result in exact output frequencies.
6.1.6 Step 6
For step 6, enter the desired DPLL loop bandwidth.
Note: Any time an approximate symbol is shown, a tool tip will allow exact output frequency to be seen by
mousing over the control.
Figure 6-5. Step 6: PLLs
6.1.7 Step 7
To calculate the DPLL divider settings, select which DPLL loop filters and dividers to calculate and press the Run
Script button. The software will now run and calculate the necessary settings.
Figure 6-6. Step 7: Run Script
6.2 Using the Status Page
The status page shows fields pertaining to the current status of the device. The update these fields click the
Read Status Bits
button or the
Read RO Regs
button in the tool bar. The Read RO Regs button will read all read
only registers which provides more information on other pages including the status fields but can take longer to
read back. The read status bits just reads the status bits for this page.
For the DPLL to lock, a reference must be validated and selected as shown in the Active Reference/Holdover
and Reference Validated portion of the window, as seen in the circled portion of
As the DPLL locks, it is expected to see the LOPL_DPLLx as the last bit to become clear when the phase lock is
acquired.
When INT_EN = 1, any live status flag which occurs will latch to the INTR Latched bit columns. These will
remain asserted until the
Clear Latched Bits
button is selected. This gives additional insight into the behavior of
the device.
Pressing the Soft-chip reset button in the toolbar will cause the device to reset and re-start lock.
Appendix A - TICS Pro LMK5C33216 Software
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LMK5C33216EVM User's Guide
SNAU260A – OCTOBER 2020 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated
