Revised – March 2014
LMX248x Evaluation Board User’s Guide
SNAU137
21
Copyright © 2014, Texas Instruments Incorporated
RF PLL Lock Time (With a Specturm Analyzer)
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The first step is to tune the PLL to the
final frequency. On the spectrum
analyzer, set span to 0 Hz and the
frequency to the final frequency. Then
set the resolution bandwidth. If it is too
small, then it will make your lock time
look longer. If it is too large, frequency
resolution is lost. For this measurement,
30 kHz seems just about right. Now
adjust the sweep time to match the time
interval for the lock time measurement,
3 mS in this case. The power is –9.6
dBm
Now tune the PLL slightly off frequency.
If the PLL is tuned 10 kHz off frequency,
the output power drops to –11.1 dBm.
So when the output power is –11.1 dBm
or higher, we are theoretically within 10
kHz. If the PLL can not be tuned to fine
enough resolution, the center frequency
of the spectrum analyzer can also be
offset.
Using the external trigger to trigger off
the LE pulse, we measure the time it
takes to get and stay high enough in
power to be about 720 uS to a 10 kHz
tolerance.
If the timeout counter is set to zero to
disable cycle slip reduction, the lock time
increases to 2145 us. So cycle slip
reduction is very worthwhile, considering
it uses no external components and
requires no additional software
overhead, once the part is set up.