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Reduced Power Modes

2-36

The power consumed during sleep when the RTO oscillator is left running is
greater than the power consumed during sleep when the CRO oscillator is left
running.

If the idle state clock control is clear, then the PLL circuitry, active during sleep,
will attempt to regulate the MC to whatever frequency is programmed in the
PLL multiplier (see Section 2.9.3,

Clock Speed Control Register). The MC con-

tinues to run at this frequency, even during sleep, provided that the reference
oscillator is enabled.

If the idle state clock control is set, then neither the MC, CPU clock, nor the
TIMER clocks run during sleep, unless the TIMER source is linked to the
reference oscillator (Section 2.8, Time Registers). These relationships are
shown explicitly, as a function of the reduced power mode, in Table 2–4.

Because the DAC circuitry is the single most source of power consumed on
the C614, it is important to disable the DAC entirely before engaging any IDLE
instruction. This is accomplished at the DAC control register, address 0x34.
Refer to Section 3.2.2,

DAC Control and Data Registers.

The ARM bit is another important control to consider before engaging the
reduced power mode. It is recommended that the ARM bit be cleared
whenever the idle state clock control is clear, and set whenever the idle state
clock control is set Table 2–3. The set ARM bit causes an asynchronous
response to all programmable interrupts when in the sleep state. (The cleared
ARM bit yields the standard synchronous response at all times.) Affected
interrupts include those tied to TIMER1 and TIMER2, as well as those tied to
the inputs at Ports F, D

2

, D

3

, D

4

, and D

5

. The advantage to having the ARM

bit set is that the device may be awakened by one of these interrupts, even
when the PLL clock circuitry is stopped in sleep (by virtue of the idle state
control). The disadvantage of the asynchronous response, however, is that it
can render irregularities in the timing of response to these same inputs.

Note:

Idle State Clock Control Bit

If the idle state clock control bit is set and the ARM bit is clear, the only event
that can wake the C614 after an IDLE instruction is a hardware RESET low-
to-high. When at sleep, the device will not respond to the input ports, nor to
the internal timers.

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Summary of Contents for MSP50C614

Page 1: ...MSP50C614 Mixed Signal Processor User s Guide SPSU014 January 2000 Printed on Recycled Paper ...

Page 2: ...CONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to ...

Page 3: ...0C605 which are in the Product Preview stage of development How to Use This Manual This document contains the following chapters Chapter 1 Introduction to the MSP50C614 Chapter 2 MSP50C614 Architecture Chapter 3 Peripheral Functions Chapter 4 Assembly Language Instructions Chapter 5 Code Development Tools Chapter 6 Applications Chapter 7 Customer Information Appendix A MSP50C605 Preliminary Data A...

Page 4: ...me address asect is the directive This directive has two parameters indicated by sec tion name and address When you use asect the first parameter must be an actual section name enclosed in double quotes the second parameter must be an address Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brack...

Page 5: ...rated by commas Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a ...

Page 6: ...vi ...

Page 7: ...s Unit 2 11 2 3 1 RAM Configuration 2 12 2 3 2 Data Memory Addressing Modes 2 13 2 4 Program Counter Unit 2 14 2 5 Bit Logic Unit 2 14 2 6 Memory Organization RAM and ROM 2 15 2 6 1 Memory Map 2 15 2 6 2 Peripheral Communications Ports 2 16 2 6 3 Interrupt Vectors 2 18 2 6 4 ROM Code Security 2 19 2 6 5 Macro Call Vectors 2 22 2 7 Interrupt Logic 2 22 2 8 Timer Registers 2 26 2 9 Clock Control 2 2...

Page 8: ...h Register PH 4 4 4 2 7 Product Low Register PL 4 4 4 2 8 Accumulators AC0 AC31 4 4 4 2 9 Accumulator Pointers AP0 AP3 4 5 4 2 10 Indirect Register R0 R7 4 5 4 2 11 String Register STR 4 6 4 2 12 Status Register STAT 4 6 4 3 Instruction Syntax and Addressing Modes 4 8 4 3 1 MSP50P614 MSP50C614 Instruction Syntax 4 8 4 3 2 Addressing Modes 4 9 4 3 3 Immediate Addressing 4 13 4 3 4 Direct Addressing...

Page 9: ...2 5 2 MSP50C6xx Software Development Tool 5 3 5 3 Requirements 5 4 5 4 Hardware Installation 5 5 5 5 Software Installation 5 6 5 6 Software Emulator 5 13 5 6 1 The Open Screen 5 13 5 6 2 Projects 5 15 5 6 3 Description of Windows 5 16 5 6 4 Debugging a Program 5 22 5 6 5 Initializing Chip 5 27 5 6 6 Emulator Options 5 28 5 6 7 Emulator Online Help System 5 30 5 6 8 Known Differences Incompatibilit...

Page 10: ... Code 6 8 6 3 1 Memory Overlay 6 13 6 4 ROM Usage With Respect to Various Synthesis Algorithms 6 14 7 Customer Information 7 1 7 1 Mechanical Information 7 2 7 1 1 Die Bond Out Coordinates 7 2 7 1 2 Package Information 7 3 7 2 Customer Information Fields in the ROM 7 7 7 3 Speech Development Cycle 7 8 7 4 Device Production Sequence 7 8 7 5 Ordering Information 7 10 7 6 New Product Release Forms 7 ...

Page 11: ...Contents xi Contents B 3 5 Host Write Sequence B 5 B 3 6 Host Read Sequence B 5 B 3 7 Interrupts B 7 B 4 Packaging B 8 C MSP50C605 Data Sheet C 1 C 1 MSP50C605 Data Sheet C 2 ...

Page 12: ...rmance 2 30 2 10 Instruction Execution and Timing 2 34 3 1 PDM Clock Divider 3 10 3 2 Relationship Between Comparator Interrupt Activity and the TIMER1 Control 3 15 4 1 Top of Stack TOS Register Operation 4 3 4 2 Relative Flag Addressing 4 19 4 3 Data Memory Organization and Addressing 4 45 4 4 Data Memory Example 4 47 4 5 FIR Filter Structure 4 59 4 6 Setup and Execution of MSP50P614 MSP50C614 Fi...

Page 13: ... 5 23 5 25 EPROM Programming Dialog 5 25 5 26 Trace Mode 5 26 5 27 Init Menu Option 5 27 5 28 Options Menu 5 29 5 29 Miscellaneous Dialog 5 29 5 30 Windows Menu Options 5 30 5 31 Context Sensitive Help System 5 31 7 1 100 Pin PJM Mechanical Information 7 4 7 2 120 Pin Grid Array Package for the Development Device P614 7 5 7 3 120 Pin Grid Array PGA Package Leads P614 7 6 7 4 Speech Development Cyc...

Page 14: ...on 4 10 4 5 MSP50P614 MSP50C614 Addressing Modes Summary 4 11 4 6 Auto Increment and Auto Decrement Modes 4 11 4 7 Flag Addressing Field flagadrs for Certain Flag Instructions Class 8a 4 12 4 8 Initial Processor State for the Examples Before Execution of Instruction 4 13 4 9 Indirect Addressing Syntax 4 15 4 10 Symbols and Explanation 4 22 4 11 Instruction Classification 4 23 4 12 Classes and Opco...

Page 15: ...ass 9b Instruction Description 4 43 4 38 Class 9c Instruction Description 4 44 4 39 Class 9d Instruction Description 4 44 4 40 Data Memory Address and Data Relationship 4 46 4 41 MSP50P614 MSP50C614 Computational Modes 4 50 4 42 Hardware Loops in MSP50P614 MSP50C614 4 54 4 43 Initial Processor State for String Instructions 4 55 4 44 Lookup Instructions 4 57 4 45 Auto Increment and Decrement 4 73 4...

Page 16: ...R Using the OUT Instruction 2 24 Interrupt Service Branch 2 24 Writing to the TIM Register 2 27 ClkSpdCtrl Bits 8 and 9 2 31 Reference Oscillator Stopped by Programmed Disable 2 32 Register Trim Value 2 33 Idle State Clock Control Bit 2 36 Reading the Data Register 3 2 PDM Enable Bit 3 9 IntGenCtrl Register Bit 15 3 16 Internal RAM State after Reset 3 20 Stack Pointer Initialization 3 21 Data Memo...

Page 17: ...ives the C614 unprecedented speed and computational flexibility compared with previous devices of its type The C614 supports a variety of speech and audio coding algorithms providing a range of options with respect to speech duration and sound quality Topic Page 1 1 Features of the C614 1 2 1 2 Applications 1 3 1 3 Development Version P614 1 4 1 4 Functional Description 1 5 1 5 C605 and C604 1 6 1...

Page 18: ...P LPC and ADPCM Contains 32K words onboard ROM 2K words reserved 640 words RAM 40 general purpose bit configurable I O 8 inputs with programmable pullup resistors and a dedicated interrupt key scan 16 dedicated output pins Direct speaker driver 32 Ω PDM One bit comparator with edge detection interrupt service IMPORTANT Not currently supported Resistor trimmed oscillator or 32 kHz crystal reference...

Page 19: ...low power needs and high programmability the C614 is suitable for a wide variety of applications incorporating I O control and high quality speech Talking Toys Talking Books Electronic Learning Aids Talking Dictionaries Games Warning Systems Talking Clocks Equipment for the Handicapped ...

Page 20: ...hout programming the EPROM However the rate of code execution is lim ited by the speed of the PC parallel port Any MSP50C614 MSP50P614 can be used in this debugging mode The MSP50P614 EPROM must be programmed to debug the code in real time The MSP software development tool is used to program the EPROM set a breakpoint and evaluate the internal registers after the breakpoint is reached If a change ...

Page 21: ...m clock and algorithm acquisition frequency A flexible clock generation system is included that enables the software to control the clock over a wide frequency range The implementation uses a phase locked loop PLL circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable Selectable frequencies for the processor clock are spaced apart in 65 536 kHz...

Page 22: ...ns The C605 can provide up to 30 minutes of uninterrupted speech The C604 is designed to support slave operation with an external host microcontroller In this mode the C604 can be programmed with a code that communicates with the host via a command set This command set can be de signed to support LPC CELP MELP and ADPCM coders by selecting the ap propriate command The C604 can also be used stand a...

Page 23: ... x 16 1 bit Test Area reserved 0x0000 to 0x07FF User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF Core Instr Decoder PCU Prog Counter Unit CU Computational Unit TIMER1 PRD1 0x3A TIM1 0x3B TIMER2 PRD2 0x3E TIM2 0x3F Clock Control 0x3D Gen Control 0x38 Interrupt Processor FLAG 0x39 MASK 0x38 DMAU Data Mem Addr RAM 640 x 17 bit data 0x000 to 0x027F A port I O Data 0x00 Control 0x04 B port I O Da...

Page 24: ... 22 pF 22 pF 10 MΩ 10 MΩ 32 768 kHz Keep these components as close as possible to the OSCIN OSCOUT and PLL pins a Crystal Oscillator Operation Connections b Resistor Trim Operation Connections MSP50C614 MSP50P614 OSCIN OSCOUT PLL R RTO 470 kΩ 1 C PLL 3300 pF Keep these components as close as possible to the OSCIN OSCOUT and PLL pins ...

Page 25: ...Ω To Pin 2 of optional scan port connector IN914 MSP50P614 only If it is necessary to use the software development tools to control the MSP50P614 in application board the 1 kΩ resistor is need ed to allow the development tool to over drive the RESET circuit on the application board This Diode can be omitted shorted if the application does not require use of the scanport interface See Section 7 1 1...

Page 26: ...ort Control Signals SCANIN 54 I Scan port data input SCANOUT 50 O Scan port data output SCANCLK 53 I Scan port clock SYNC 52 I Scan port synchronization TEST PGMPULSE 51 I C614 test modes P614 programming pulse The scan port pins must be bonded out on any C614 production board Consult the Important Note regarding Scan Port Bond Out Section 7 1 1 Scan Port Bond Out Oscillator Reference Signals OSCI...

Page 27: ... VCC4 27 GND 52 NC 77 NC 3 NC 28 NC 53 NC 78 NC 4 NC 29 NC 54 NC 79 DACM 5 PG7 30 NC 55 NC 80 VCC3 DA 6 PF6 31 X2 56 NC 81 DACP 7 PF5 32 X1 57 NC 82 VCC 8 PF4 33 PLL 58 PC7 83 PF7 9 PF3 34 PA7 59 PC6 84 PF6 10 PF2 35 PA6 60 PC5 85 PF5 11 PF1 36 PA5 61 PC4 86 PF4 12 PF0 37 PA4 62 PC3 87 PF3 13 SCANOUT 38 PA3 63 PC2 88 PF2 14 TEST 39 PA2 64 PC1 89 PF1 15 SYNC 40 PA1 65 PC0 90 PF0 16 SCANCLK 41 PA0 6...

Page 28: ...0 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 NC NC NC PB0 PB2 PB3 PB4 PB5 PB6 PB7 1 GND1 PA0 PA2 PA1 PA5 PA6 PA7 PLL X1 X2 GND3 DA NC NC DACM DACP PF7 PF5 PF4 PF2 PF1 PF0 NC PG15 PG14 PG13 PG12 PG10 PG9 PD1 PD2 PD4 PD5 PD6 PD7 PC1 PC5 PC6 PC7 NC NC PG6 PG5 PG4 PG3 PG2 PG1 PG0 TEST SYNC SCANIN RESET PE7 PE6 PE5 PE3 PE2 CC V PE4 PJM PACKAGE TOP VIEW NC PC3 GND2 PC0 NC PA4 SCANCLK PF6 P...

Page 29: ...le The P614 s PGA package is shown in Figure 1 5 and Table 1 3 Figure 1 5 120 Pin Grid Array Package for the Development Device P614 12 13 10 11 8 9 6 7 N M K L J H 4 2 3 F E C B D A 1 G 5 N M K L J H F E C B D A G 2 1 4 3 6 5 8 7 10 12 11 13 9 extra pin bottom view top view MSP50P614 Note PGA Package The PGA package is only available in limited quantities for development pur poses ...

Page 30: ...anout H VDD PD7 PD6 pgmpuls SYNC scanclk G VSS PC1 PC0 bottom view RESET scanin PE7 F PC2 PC3 PC4 PE4 PE5 PE6 E PC5 PC6 nc PE0 PE2 PE3 D PC7 nc nc extra nc VSS PE1 C nc nc nc nc PB1 PB5 VSS PA3 PA7 nc nc nc nc B nc nc nc PB0 PB3 PB6 PA0 PA2 PA5 PLL OSCOUT nc nc A nc nc nc PB2 PB4 PB7 VDD PA1 PA4 PA6 OSCIN nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 It is important to provide a separate decoupling capacito...

Page 31: ...interrupt system timers clock control mecha nism and various low power modes Topic Page 2 1 Architecture Overview 2 2 2 2 Computation Unit 2 5 2 3 Data Memory Address Unit 2 11 2 4 Program Counter Unit 2 14 2 5 Bit Logic Unit 2 14 2 6 Memory Organization RAM and ROM 2 15 2 7 Interrupt Logic 2 22 2 8 Timer Registers 2 26 2 9 Clock Control 2 29 2 10 Execution Timing 2 33 2 11 Reduced Power Modes 2 3...

Page 32: ...nipulation A unique accumulator register file provides additional scratch pad memory and minimizes memory thrashing for many operations Five different addressing modes and many short direct references provide enhanced execution and code efficiency The basic elements of the C614 core are shown in Figure 2 1 In addition to the main computational units the core s auxiliary functions include two timer...

Page 33: ...ister CTRL Interrupt Inputs Interrupt Processor Serial Interface Register Oscillator Register Timer Period PRD1 and PRD2 Timer Register TIM1 and TIM2 AP0 AP3 Accumulator Pointer Incrementor 1 Peripheral Interface Instruction Decoder Frequency Divider VCO Serial Interface Top Of Stack TOS Program Counter PC Protection Register PR Data Pointer DP MUX String Register MUX Repeat Counter Status Registe...

Page 34: ...ead Write AC7 AC6 AC5 AC4 AC11 AC10 AC9 AC8 AC15 AC14 AC13 AC12 AC19 AC18 AC17 AC16 AC23 AC22 AC21 AC20 AC27 AC26 AC25 AC24 AC31 AC30 AC29 AC28 AP3 AP2 AP1 AP0 5 Internal Databus 16 bit Shift Value SV Multiplier Register MR 17 bit x 17 bit Multiplexer Product High PH 16 16 16 MSB 16 16 16 16 16 16 0 16 Product Low PL 16 LSB 16 ALU A B 16 0 16 ...

Page 35: ...a single instruction cycle The sign bit within each operand is bit 16 and its value extends from bit 0 LSB to bit 15 MSB The sign bit for either operand multiplier or multiplicand can assume a positive value zero or a value equal to the MSB bit 15 In assuming zero the extra bit supports unsigned multiplication In assuming the value of bit 15 the extra bit supports signed multiplication Table 2 1 s...

Page 36: ...plicand The output result is 32 bit On the other hand if the status bit FM multiplier shift mode is SET then the multiplier operand 0000000010000000 is left shifted once to form a 17 significant bit operand 00000000100000000 This mode is included to avoid a divide by 2 of the product when interpreting the input operands as signed binary fractions The multiplier shift mode status bit is located in ...

Page 37: ...2 2 Arithmetic Logic Unit The arithmetic logic unit is the focal point of the computational unit where data can be added subtracted and compared Logical operations can also be performed by the ALU The basic hardware word length of the ALU is 16 bits however most ALU instructions can also operate on strings of 16 bit words i e a series or array of values The ALU operates in conjunction with a flexi...

Page 38: ...erations are addition subtraction and load add to zero The logical operations are AND OR XOR and NOT Comparison includes equal to and not equal to The compare operations may be used with constant memory or string values without destroying any accumulator values 2 2 2 1 Accumulator Block The output of the ALU is the accumulator block The accumulator block is com posed of 32 16 bit registers These r...

Page 39: ...AC31 For multiply accumulate operations 2 2 2 2 Accumulator Pointer Block There are four 5 bit registers which are used to store pointers to members of the accumulator block The accumulator pointers AP0 AP1 AP2 AP3 are used in two modes 1 as a direct reference to one of 32 or 2 as an indirect reference The indirect reference includes a direct reference to one of 16 and an offset optional which inc...

Page 40: ...in one of two forms 1 DIRECT REFERENCE 0 31 AC Register 2 INDIRECT REFERENCE 0 15 points to 0 15 0 15 OFFSET points to 16 31 15 31 OFFSET points to 0 15 AP registers are served by a 5 bit processor for sequencing addresses or repetitive operations Selection between the 4 AP s is made in the 2 bit An field in all accumulator referenced instructions 2 2 2 3 String Operations The AP registers are ser...

Page 41: ... accumula tor register Refer to Chapter 4 Instructions for more details The ALU s accumulator block functions as a small workspace which elimi nates the need for many intermediate transfers to and from memory This al leviates the memory thrashing which frequently occurs with single accumula tor designs 2 3 Data Memory Address Unit The data memory address unit DMAU provides addressing for data memo...

Page 42: ...ically the flag bit directs complex branch conditions associated with certain instructions The flag bit is also used by the computational unit for signed or unsigned arithmetic operations see Section 2 2 1 Multiplier The size of the C614 RAM block is 640 17 bit locations Each address provided by the DMAU causes 17 bits of data to be addressed These 17 bits are operated on in different ways dependi...

Page 43: ... whereby 64 global flags are located at fixed locations in the first 64 RAM addresses and 2 flag relative address whereby a reference is made relative to the current PAGE R6 The relative address supports 64 different flags whose PAGE offset values are stored in the PAGE register The flag mode instructions cannot address memory in the INDEX relative modes See Chapter 4 Instructions for more details...

Page 44: ... Address Unit The hardware loop counter controls the execution of repeated instructions using one of two modes 1 consecutive iterations of a single instruction following the repeat RPT instruction or 2 a single instruction which operates on a string of data values string loops For all types of repeated execution interrupt service branches are automatically disabled temporarily The data pointer DP ...

Page 45: ...its of the 17 bit RAM are used for the data value while the extra bit is used as a status flag The C614 does not have the capability to execute instructions directly from external memory However additional program memory external ROM can be accessed using the general purpose I O The interface for external ROM must be configured in the software 2 6 1 Memory Map The memory map for the C614 is shown ...

Page 46: ...data 0x30 DAC data 0x34 DAC ctrl 0x38 IntGenCtrl 0x39 IFR 0x3A PRD1 0x3B TIM1 0x3D ClkSpdCtrl 0x3E PRD2 0x3F TIM2 0x2F RTRIM Unusable Interrupt Vectors reserved RESET vector 0x7FF8 0x7FFE 0x7FFF Shaded boxes highlight dedicated ROM and control registers 2 6 2 Peripheral Communications Ports Peripheral functions in the C614 are controlled using one or more of the I O address mapped communications p...

Page 47: ...ress Width of Location Allowable Access Control Register Name Abbreviation State after RESET LOW Section for Reference 0x00 8 bits read write I O port A data PA0 7 Data unknown 0x04 8 bits read write I O port A control PA0 7 Ctrl 0x00 0x08 8 bits read write I O port B data PB0 7 Data unknown 0x0C 8 bits read write I O port B control PB0 7 Ctrl 0x00 0x10 8 bits read write I O port C data PC0 7 Data...

Page 48: ...he interrupt vector which resides in an up per address of ROM The following table lists the ROM address associated with each interrupt vector Interrupt Name ROM address of Vector Event Source Interrupt Priority INT0 0x7FF0 DAC Timer Highest INT1 0x7FF1 TIMER1 2nd INT2 0x7FF2 TIMER2 3rd INT3 0x7FF3 port D2 4th INT4 0x7FF4 port D3 5th INT5 0x7FF5 all port F 6th INT6 0x7FF6 port D4 7th INT7 0x7FF7 po...

Page 49: ...an arbitrary address The two levels of ROM protection are designated as follows Direct read and write protection via the ROM scan circuit Indirect read protection which prohibits the execution of memory lookup instructions For the purposes of direct security the ROM is divided into two blocks The first block begins at location 0x0000 and ends inclusively at location m 512 1 where m is some integer...

Page 50: ...E 17 bit wide location WRITE only 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 R R TM TM TM TM TM TM GP BP R FM FM FM FM FM FM 05 04 03 02 01 00 05 04 03 02 01 00 TM True Protection Marker NTM GP Global Protection 0 value protects FM False Protection Marker NFM BP Block Protection 0 value protects R Reserved for future use must be 1 1 Default value of cells on erasure The two 6 bit fields ar...

Page 51: ...ection Mode When applying the block protection mode bits FM5 through FM0 must be programmed as the logical inverse of bits TM5 through TM0 respectively Across the span of the 32k word ROM space there are 64 possible values for NTM including zero Hence the 6 bit wide locations for TM and FM The two single bit fields found within the block protection word are the block protection bit BP and the glob...

Page 52: ... 4 14 83 VCALL for more information on the VCALL instruction 2 7 Interrupt Logic An eight level interrupt system is included as part of the C614 s core processor The initialization and control of these interrupts is governed by the following components the global interrupt enable the interrupt flag register the interrupt mask register and the interrupt service branch Each of these is described bel...

Page 53: ...vice by setting or clearing the respective bit in the interrupt mask register IMR 8 bits If an interrupt level has its bit cleared in the IMR then the interrupt service associated with that interrupt is disabled Setting the bit in the IMR allows service to occur pending the trigger event which is registered in the IFR The IMR is accessible as part of another larger register namely the interrupt ge...

Page 54: ...entually the program returns to whatever point it was before the first interrupt service branch When an interrupt service branch is taken the global interrupt enable is automatically cleared by the core processor This disables all further interrupt service branches while still in the pending service routine As a result the programmer must re enable the interrupts globally using the INTE instructio...

Page 55: ...IT INT Flag bits IFR Associated With the Interrupt Trigger Event Interrupt Flag Register 0x39 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 CLEAR BIT INT Mask bits IMR Specific Enable for Interrupt Service Interrupt General Control Register 0x38 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Interrupt Service Branch Highest Priority INT is Selected From Among Those Flagged and Enabled Program Branches to Locat...

Page 56: ...r and the count down register TIM1 or TIM2 does the counting When the count down register decrements to the value 0x0000 then the value currently stored in the period register is loaded to the count down register The count down register then resumes counting again from that value For each TIMER there is an interrupt trigger event associated with the TIMER s underflow condition the point of reachin...

Page 57: ...until the TIM register has finished decrementing to 0x0000 The new value in the PRD register is then loaded to the TIM register and counting resumes from the new value Note Writing to the TIM Register Writing to the TIM register causes the same value to be written to the PRD register In this case the TIM register is immediately updated and counting continues immediately from the new value Each TIM...

Page 58: ...t for TIMER1 and bit 11 is the enable bit for TIMER2 Setting the enable bit enables the TIMER i e starts count down running Clearing the enable bit disables the TIMER i e stops the count down The default setting after a RESET LOW is zero both TIMERs disabled Refer to Section 3 4 Interrupt General Control Register for sum mary information regarding the IntGenCtrl The TIMER enable bits may be used t...

Page 59: ...xternally across pins OSCIN and OSCOUT 2 9 2 PLL Performance A software controlled PLL multiplies the reference frequency generated from either RTO or CRO by integer multiples This higher frequency drives the master clock which in turn drives the CPU clock The master clock MC drives the circuitry in the periphery sections of the C614 The CPU Clock drives the core processor its rate determines the ...

Page 60: ...plier Adjusted in ClkSpdCtrl x 1 x 256 x4 Timer Source Option Selected in IntGenCtrl 1 0 TIMER2 1 0 TIMER2 2 MC Master Clock Runs Periphery 131 07 kHz 33 554 MHz 2 CPU Clock Core Processor Speed 65 536 kHz FMAX FMAX 8 MHz 2 9 3 Clock Speed Control Register The ClkSpdCtrl is a 16 bit memory mapped register located at address 0x3D The reference oscillator RTO or CRO is selected by setting one of the...

Page 61: ...ferences RTO or CRO is enabled in software Refer to Chapter 8 MSP50C614 Electrical Specifications for a more precise characterization of the master clock rate under these conditions Once a reference oscillator has been enabled the speed of the master clock MC can be set and adjusted as desired Bits 7 through 0 in the ClkSpdCtrl constitute the PLL multiplier PLLM The value written to the PLLM contr...

Page 62: ...rim the RTO to its rated 32 kHz specification The correct trim value varies from device to device The user must program bits 15 through 11 and 9 in order to achieve the 32 kHz specification within the rated tolerances Texas Instruments provides the trim value to the programmer of the P614 part with a sticker on the body of the chip For the C614 part the correct trim value is located at I O locatio...

Page 63: ...same chip Note Register Trim Value A resistor trim value is only needed when the resistor trimmed oscillator RTO is used The MSP50P614 device must determine the trim value sepa rately and use this value in the ClkSpdCtrl register bits 15 11 and 9 but C614 device needs to copy bit 0 of I O location 0x2F to bit 9 of the ClkSpdCtrl regis ter and bits 5 through 1 to bits 15 through 11 of ClkSpdCtrl re...

Page 64: ...trical Specifications for a full description of the electrical characteristics including the acceptable power supply ranges The reduced power state on the C614 is achieved by a call to the IDLE instruction The idle state is released by some interrupt event Different modes or levels of reduced power are brought about by controlling a number of different core and periphery components on the device T...

Page 65: ...p Setting the idle state control causes the CPU clock the PLL clock circuitry and the MC to stop after the next IDLE instruction Clearing the idle state control causes only the CPU clock to stop after IDLE The PLL clock circuitry governs the MC and determines its rate Whenever the PLL circuitry is suspended therefore the MC stops The idle state clock control is accessed at bit 10 in the ClkSpdCtrl...

Page 66: ...ss 0x34 Refer to Section 3 2 2 DAC Control and Data Registers The ARM bit is another important control to consider before engaging the reduced power mode It is recommended that the ARM bit be cleared whenever the idle state clock control is clear and set whenever the idle state clock control is set Table 2 3 The set ARM bit causes an asynchronous response to all programmable interrupts when in the...

Page 67: ...SpdCtrl register 0x3D A 0 1 1 Enable reference oscillator bit 09 CRO or bit 08 RTO ClkSpdCtrl register 0x3D B 1 1 0 ARM bit 14 IntGenCtrl register 0x38 C 0 1 1 Enable PDM pulsing bit 02 DAC Control register 0x34 D Should be cleared before any IDLE instruction IDLE instruction executes the mode E Same instruction is used to engage any of the modes PLL multiplier bits 07 through 00 ClkSpdCtrl regist...

Page 68: ... than the time delay required for the RTO to start There are a number of ways to wake the C614 from the IDLE induced sleep state The various options are summarized as a function of the reduced power mode in Table 2 5 Naturally the RESET event happens after the RESET pin has gone low to high causes an immediate escape from sleep whereby the program counter assumes the location stored in the RESET i...

Page 69: ...No wake up from TIMER External interrupts Port F and D2 3 4 5 if input Assuming respective IMR bit is set Assuming ARM bit is set as in C C Rising Edge or Falling Edge as appropriate wakes device RESET none RESET LOW to HIGH always wakes device DAC Timer Assuming PDM bit is clear as in D D No wake up from DAC Timer The external interrupt is the other programmable option for waking the C614 from sl...

Page 70: ...ediately following the IDLE instruction which initiated the sleep This type of wake up response may be useful for putting the C614 into a hold sleep whereby any number of programmable interrupts can wake the device yet they all return the program to the very same location In order to accomplish this each of the necessary interrupts should be enabled in the IMR The global interrupt enable however i...

Page 71: ...control ports general purpose I O ports interrupt control registers compara tor and digital to analog DAC control mechanisms Topic Page 3 1 I O 3 2 3 2 Digital to Analog Converter DAC 3 8 3 3 Comparator 3 14 3 4 Interrupt General Control Register 3 17 3 5 Hardware Initialization States 3 19 Chapter 3 ...

Page 72: ...dress of the data register as an argument When configured as an output the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the associated data register This is done using the OUT instruction with the address of the data register as an argument Port A Port B Port C Port D Port E Control register address 0x04h 0x0Ch 0x14h 0x1Ch 0x24h Possible control val...

Page 73: ...3 B2 B1 B0 B port control register address 0x0C C C C C C C C C C port data register address 0x10 C7 C6 C5 C4 C3 C2 C1 C0 C port control register address 0x14 C C C C C C C C D port data register address 0x18 D7 D6 D5 D4 D3 D2 D1 D0 D port control register address 0x1C C C C C C C C C E port data register address 0x20 E7 E6 E5 E4 E3 E2 E1 E0 E port control register address 0x24 C C C C C C C C A7 ...

Page 74: ...llups After RESET low the default setting for the EP bit is 0 F port pullups disabled Input Port F Data register address 0x28h Possible input data values Low 0 High 1 Possible output data values N A Value after RESET low Pullup resistors DISABLED When reading from the 8 bit F port data register to a 16 bit accumulator the IN instruction automatically clears the extra bits in excess of 8 The desire...

Page 75: ...dress as an argument Af ter RESET low the default settings for the G port outputs are 0 logical low Totem Pole Output Port G Data register address 0x2Ch Possible input data values N A Possible output data values 0 Low 1 High Value after RESET low 0 Low The following table shows the bit locations of the port G address mapping G port Data address 0x2C read and write 16 bit wide location 15 14 13 12 ...

Page 76: ...en has its conditional jump ignored has its conditional jump taken COND2 may be associated instead with the comparator function if the comparator Enable bit is set Please refer to Section 3 3 Comparator for details 3 1 5 Internal and External Interrupts INT3 INT4 INT6 and INT7 are external interrupts which may be triggered by events on the PD2 PD3 PD4 and PD5 pins These interrupts are supported wh...

Page 77: ...Event Priority Comment INT0 0x7FF0 DAC Timer Timer underflow Highest Used to synch speech data INT1 0x7FF1 TIMER1 Timer underflow 2nd INT2 0x7FF2 TIMER2 Timer underflow 3rd INT3 0x7FF3 PD2 Rising edge 4th Port D2 goes high INT4 0x7FF4 PD3 Falling edge 5th Port D3 goes low INT5 0x7FF5 All port F Any falling edge 6th Any F port pin goes from all high to low INT6 0x7FF6 PD4 Rising edge 7th Port D4 go...

Page 78: ... are 7 2 kHz 8 kHz 10 kHz and 11 025 kHz Other sampling rates however may also be possible From the MC to the PDM clock there is an optional divide by two in frequency This option is controlled by the PDM clock divider in the interrupt general control register This means that the PDM rate can be set to run between 131 07 kHz and 33 554 MHz in 131 07 kHz steps the same as the MC Or the PDM rate can...

Page 79: ...unction is off Data values are output to the DAC by writing to the DAC data register address 0x30 The highest priority interrupt INT0 is generated at the sampling rate governed by the ClkSpdCtrl and the DAC control register The program in software is responsible for writing a correctly scaled DAC value to the DAC data register in response to each INT0 interrupt The register at 0x30 is 16 bits wide...

Page 80: ...ure that the audible artifacts of wrap around do not occur 3 2 3 PDM Clock Divider The pulse density modulation rate is determined by the master clock The PDM rate may be set equal to the rate of the MC or it may be set at one half the rate of the MC This option is controlled by the PDM clock divider PDMCD in the interrupt general control register IntGenCtrl The PDMCD is located at bit 13 in IntGe...

Page 81: ...ting filter computation then a return to the main program As stated previously the maximum ensured CPU clock frequency for the C614 operates over the entire VDD range This rate applies to the speed of the core processor Operating the processor higher than the listed specification is not recommended by Texas Instruments The following tables illustrate a number of possible combinations with respect ...

Page 82: ...1 05 8 19 128 128 2x 0x 1E 4 06 4 06 2 03 15 87 128 256 4x 0x 3E 8 26 8 26 4 13 32 26 128 512 8x 0x 7C 16 38 16 38 8 19 64 00 128 1024 0 1x 0x 1E 4 06 2 03 2 03 7 94 256 256 2x 0x 3E 8 26 4 13 4 13 16 13 256 512 4x 0x 7C 16 38 8 19 8 19 32 00 256 1024 9 bits 1 1x 0x 1E 4 06 4 06 2 03 7 94 256 256 2x 0x 3E 8 26 8 26 4 13 16 13 256 512 4x 0x 7C 16 38 16 38 8 19 32 00 256 1024 0 1x 0x 3E 8 26 4 13 4 ...

Page 83: ...62 1 31 10 24 128 128 2x 0x 26 5 11 5 11 2 56 19 97 128 256 4x 0x 4D 10 22 10 22 5 11 39 94 128 512 8x 0x 9B 20 45 20 45 10 22 79 87 128 1024 0 1x 0x 26 5 11 2 56 2 56 9 98 256 256 2x 0x 4D 10 22 5 11 5 11 19 97 256 512 4x 0x 9B 20 45 10 22 10 22 39 94 256 1024 9 bits 1 1x 0x 26 5 11 5 11 2 56 9 98 256 256 2x 0x 4D 10 22 10 22 5 11 19 97 256 512 4x 0x 9B 20 45 20 45 10 22 39 94 256 1024 0 1x 0x 4D...

Page 84: ...has its conditional jump ignored 2 Steady State Comparator FALSE VPD5 VPD4 COND2 FALSE CIN2 CNIN2 has its conditional call ignored has its conditional call taken JIN2 JNIN2 has its conditional jump ignored has its conditional jump taken 3 Comparator transition FALSE to TRUE VPD5 rises above VPD4 INT6 trigger event IF INT6 Flag is SET OR INT7 Flag is CLEAR AND TIMER1 Enable is CLEAR THEN TIMER1 sto...

Page 85: ...time that the associated mask bit is SET IntGenCtrl address 0x38 bit 7 The latter indicates that the service for INT7 is enabled The INT7 Flag may also be SET or CLEARed at any time in software Use the OUT instruction with the associated I O port address IFR address 0x39 The TIMER1 enable bit is set or cleared in software bit 10 of the IntGenCtrl Similarly the falling edge event in the comparator ...

Page 86: ... Comparator ENABLED SET bit 15 in the IntGenCtrl address 0x38 PD4 functions as comparator negative input PD5 functions as comparator positive input port D Control 0x1C bit 4 MUST be 0 port D Control 0x1C bit 5 MUST be 0 COND2 maps to the state of the comparator PD5 relative to PD4 INT6 is triggered by a rising edge at PD5 INT7 is triggered by a falling edge at PD5 relative to PD4 TIMER1 may be sta...

Page 87: ...000 State after RESET low Interrupt mask register CE Comparator enable AR ARM bit PD Pulse density clock PDMCD EP Enable pullup resistors on port F D5 port D5 falling edge D4 port D4 rising edge D3 port D3 falling edge D2 port D2 rising edge E2 Enable TIMER2 1 value starts timer E1 Enable TIMER 1 1 value starts timer S2 Clock source for TIMER2 0 chooses 1 2 MC S1 Clock source for TIMER1 0 chooses ...

Page 88: ...e Section 3 2 3 PDM Clock Divider Bit 14 is the ARM bit The set ARM bit causes an asynchronous response to the internal and external interrupts during the sleep state If the master clock has been suspended during sleep then the ARM bit must be set before the IDLE instruction in order to allow a programmable interrupt to wake the C614 Refer to Section 2 11 Reduced Power Modes for more information F...

Page 89: ...t the C614 initialization occurs after the power supply has had time to stabilize between VDD MIN and VDD MAX VDD MIN and VDD MAX are the minimum and maximum supply voltages as rated for the device The circuit shown however may not shield the RESET pin from every kind of rapid fluctuation in the power supply At any time that the power supply falls below VDD MIN even momentarily then the RESET pin ...

Page 90: ...ero renders slowest speed for RTO once enabled Interrupt mask register is 0x00 Global interrupt enable is clear All Interrupts are disabled I O Ports A through E and output Port G have the same state as in RESET low All pull up resistors on input Port F are disabled DAC circuitry is disabled no PDM pulsing Both TIMER1 and TIMER2 are disabled Count down and period registers are 0x0000 The status re...

Page 91: ...0 Extended sign mode disabled 1 UM 0 Unsigned multiplier mode disabled allows signed multiplier mode 2 OM 0 Overflow mode disabled allows ALU normal mode 3 FM 0 Shift mode for fractional multiplication disabled allows unsigned fractional integer arithmetic 4 IM 0 Global interrupt enable bit 5 reserved Reserved for future use 6 XZF Transfer equal to zero status bit 7 XSF Transfer sign status bit 8 ...

Page 92: ...3 22 ...

Page 93: ...yntax and Addressing Modes 4 8 4 4 Instruction Classification 4 22 4 5 Bit Byte Word and String Addressing 4 44 4 6 MSP50P614 MSP50C614 Computational Modes 4 49 4 7 Hardware Loop Instructions 4 53 4 8 String Instructions 4 55 4 9 Lookup Instructions 4 57 4 10 Input Output Instructions 4 59 4 11 Special Filter Instructions 4 59 4 12 Conditionals 4 69 4 13 Legend 4 70 4 14 Individual Instruction Des...

Page 94: ... shift instructions the multiplier operand decodes a 4 bit value in the shift value register SV to a 16 bit value For example a value of 7H in the SV register is decoded to a multiplier operand of 0000000010000000 binary In effect this causes a left shift of 7 bits to in the final 32 bit product In other words a nonzero value say k 0 k 15 in the SV register means padding k number of zeros to the r...

Page 95: ...ter R7 The MSP50P614 MSP50C614 hardware uses TOS register for very efficient returns from CALL instructions Figure 4 1 shows the operation of the TOS register When call instructions are executed the old TOS register value is pushed into the stack by pre incrementing R7 The current PC value is incremented by 2 to compute the final return address and is then stored in the TOS register Thus the TOS r...

Page 96: ...5 have offset accumulators AC16 AC31 and vice versa At any one time four accumulators can be selected through accumulator pointer registers AP0 AP3 see section 4 2 9 Some instructions can specify offset accumulators which are the accumulators pointed to by APn 16 or APn 16 whichever is in the range 0 to 31 The offset accumulators are indicated by an offset bit A in some instructions When this bit ...

Page 97: ...ions can be performed on accumulator pointers Bit Bits 16 5 4 3 2 1 0 AP0 AP3 Not used Points to An n val b0 b4 4 2 10 Indirect Register R0 R7 Indirect registers R0 R7 are 16 bit registers that are used in various addressing modes or as general purpose registers R0 R1 R2 and R3 can be usedsolely as general purpose registers These registers can also be used as indirect registers with relative addre...

Page 98: ...ational modes Condition bits and flags are used for conditional branches calls and flag instructions Flags and status condition bits are stored in the upper 10 bits of the 17 bit status register MOV instructions provide the means for context saves and restores of the status register The STAT should be initialized to 0000h after the processor resets The XSF and XZF flags are related to data flow to...

Page 99: ...ulator and Rx registers 7 XSF Transfer x sign status flag bit In transfer instructions the sign bit of the value is copied to this bit if the destination is not accumulator or Rx registers 8 RCF Indirect register carry out status flag bit This bit is set if an addition to the value of Rx register caused a carry 9 RZF Indirect register equal to zero status flag bit This bit is set if the Rx registe...

Page 100: ...he execution of an instruction Op tional or not used for some instructions Destination is also used as both a source and a destination for some instructions If a destination is specified it must always be the first argument Destinations can be system registers or data memory locations referred by addressing modes This is instruc tion specific src source of first data Optional or not used for some ...

Page 101: ...ignificant data word in memory String data fetches using the indirect with post modification addressing mode and writes the modified address back to the indirect register at each cycle of the string This will leave the address in the Rx register pointing to the data word whose address is one beyond the most significant word of the string All addressing modes except immediate addressing are encoded...

Page 102: ...Repeat addressing mode encoding adrs Relative Addressing Modes Clocks clk Words w Repeat Operation clk adrs 7 6 5 4 3 2 1 0 Modes clk w clk am Rx x 0 7 pm Direct 2 2 nR 4 dma16 0 0 0 Rx 0 0 Short relative 1 1 nR 2 R6 offset7 1 offset7 Relative to R5 1 1 nR 2 Rx R5 0 1 0 Rx 0 0 Long relative 2 2 nR 4 Rx offset16 0 0 1 Rx 0 0 Indirect 1 1 nR 2 Rx 0 0 Rx 0 1 1 Rx 0 1 Rx 0 1 1 Rx 1 0 Rx R5 1 1 dma16 a...

Page 103: ...ffset7 next A name R6 offset7 src next A Selects PAGE R6 register as the base address and adds a 7 bit positive address offsetfromoperandfield b6 b0 This permits the relative addressing of 128 bytes or 64 words Does not modify the PAGE address register k is shown as constant Global Flag name TFn dma6 name dma6 TFn For use with flag instructions only Adds lower 7 bits of instruction to a fixed addr...

Page 104: ...address from the indirect register R6 If bit 0 of these instructions is 0 then bits 1 to 6 of the opcode are taken as the bit address starting from data memory location 0000h If bit 0 is 1 then bits 1 to 6 are used as an offset from the page register R6 to compute the relative address Bits 0 to 6 of flag instructions are written as flagadrs throughout this manual When this symbol appears it should...

Page 105: ... 0x0200 R2 0x0540 R3 0x03E2 R4 0x0000 R5 2 R6 0x03E4 R7 0x0100 AC2 0x13F0 AC1 0x0007 AC17 0x0112 AC20 0x3321 AC3 0xFEED AC28 0x11A2 AC29 0xAB AC19 0x1200 MR 0x1A15 data memory address data word address to convert to byte address multiply by 2 0x022A 0x0400 0x01F2 0x12AC 0x02A1 0x1001 0x012F 0x0000 0x0100 0x0ABC 0x0080 0x0000 0x0001 0x499A 0x01FA 0x0112 program memory address data 0x13F0 0x1B12 Exa...

Page 106: ...e 4 8 before execution of this instruc tion Preincrement AP1 After preincrement A1 is AC22 and A1 is AC6 The content of data memory location 0x01F2 0x12AC is then loaded to accumu lator AC22 offset of AC6 Final result AP1 22 AC6 0x12AC Example 4 3 7 SUB A1 A1 0x02A1 2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Predecrement AP1 After predecrement A1 is...

Page 107: ... post decrement Rx after use Address Memory Operand R5 Rx x 0 7 Note that the Rx registers treats data memory as a series of bytes Therefore when a word is loaded Rx increments by 2 Rx decrements by 2 When loading a word address into Rx the address must be converted into a byte ad dress by multiplying by 2 For example if we want Rx to point to the word ad dress 0x100 Rx should be loaded with 0x100...

Page 108: ...is instruc tion Store the lower 8 bits of A3 AC29 in the data memory byte address pointed to by R7 R7 is then incremented by one Notice that to find the word address divide the address in R7 by 2 Final result R7 0x0101 0x0100 0xAB byte address or 0x80 0xAB00 word address Example 4 3 16 OUT 0x08 R1 Refer to the initial processor state in Table 4 8 before execution of this instruc tion The contents ...

Page 109: ...2 is AC12 and A2 is AC28 Store AC28 in the data memory byte location R2 R5 The values in R2 and R5 are unchanged Final result 0x02A1 0x11A2 Example 4 3 19 ADD A0 A0 R4 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Predecrement AP0 After predecrement A0 is AC1 and A0 is AC17 Add AC1 to the contents of byte location R4 R5 and put the result in AC17 The ...

Page 110: ...Relative Long relative addressing selects one of the 8 address registers Rx as a base value and adds the value of the second word operand The base address reg ister is not modified Syntax name dest src Rx offset16 next A name Rx offset16 src next A Address Rx x 0 7 Memory Operand Operand Example 4 3 22 MOV A0 R1 0x0254 A Refer to the initial processor state in Table 4 8 before execution of this in...

Page 111: ... 17th bit This should not be confused with byte ad dresses and word addresses Figure 4 2 Relative Flag Addressing Address R6 PAGE register 6 Bit positive offset Operand Syntax name dest src Global Flag name TFn dma6 name dma6 TFn Relative Flag name TFn R6 offset6 name R6 offset6 TFn Example 4 3 24 MOV 0x02 TF2 Take the test flag 2 bit TF2 in the status register and place it into the 17th bit of th...

Page 112: ...2 2 sets the TAG bit of RAM word two STAG and RTAG use RAM byte addresses to specify which TAG to set or clear This immediately causes confusion since there are 1280 bytes and only 640 TAGs What happens when an odd byte is used to set a tag with STAG STAG 0x0001 sets the TAG bit of RAM word zero STAG 0x0003 sets the TAG bit of RAM word one STAG 0x0005 2 sets the TAG bit of RAM word five All word b...

Page 113: ...form as you would expect The TAG bit is set at the RAM variable ram1 The TAG bit is set in the STAT register when the MOV instruction executes Finally ram1 s TAG bit is cleared The next two instructions are problematic When SFLAG sets the tag bit it will set the tag bit for the second word location ram2 This does not set the TAG bit for ram1 What is worse is that the value in ram1 must be less tha...

Page 114: ...destination accumulator if this bit is 1 A Can be either A or A based on the opcode or instruction A Select offset accumulator as source if this bit is 1 adrs Addressing mode bits am Rx pm See Table 4 4 An Accumulator pointed to by APn Accumulators cannot be referenced directly For example A22 is not valid since accumulators are only addressible though the accumulator pointers AP0 AP3 Therefore to...

Page 115: ...ese bits are not related to any addres sing modes Rx Indirect register bits as described in Table 4 3 s Represents string mode if 1 otherwise normal mode x Don t care Instructions on the MSP50P614 MSP50C614 are classified based on the op erations the instruction group performs see Table 4 11 Each instruction group is referred to as a class There are 9 instruction classes Classes are subdivided int...

Page 116: ...constant fields operating on Rx and others 5 General mMemory reference instructions 6 I O port and memory reference instructions A Port memory reference B Port accumulator reference 7 Program control instructions A Macro call instructions B Conditional and unconditional jump instructions C Conditional and unconditional call instructions 8 Logical bit instructions A Logical flag instructions B Test...

Page 117: ... 0 1 0 0 An C9a 0 Rx 1 1 Class 9b 1 1 1 1 1 1 0 C9a k Class 9c 1 1 1 1 1 0 1 An 0 C9c x imm5 Class 9d 1 1 1 1 1 1 1 1 0 C9d 0 0 0 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 n NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Meaning of this bit depends on what class 3 instruction is used 4 4 1 Class 1 Instructions Memory and Accumulator Reference This class of instructions controls execution between data mem...

Page 118: ...erence to offset accumulators in Class 1b instructions the execution operates on memory and accumulators All other modes of control string preincrement predecrement AP data memory addressing modes etc are provided for logical byte multiply accumulate and barrel shift instructions Table 4 13 Class 1 Instruction Encoding Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 1a 0 0 C1a A next A An adrs ...

Page 119: ...sed on the LSB of the address Transfer status is modified 0 1 0 1 Reserved N A 0 1 1 0 CMP An adrs CMPS An adrs Store the arithmetic status of the contents of adrs subtracted from accumulator into the ALU status bits The accumulator is not modified 0 1 1 1 MOV adrs An MOVS adrs An Look up the value stored in program memory addressed by the accumulator and store in the data memory location in adrs ...

Page 120: ...16 bits to the accumulator and latch the upper 16 bits in PH ALU status is modified 1 1 1 1 MULSPL An adrs MULSPLS An adrs Multiply the MR register by the contents of adrs and subtract the lower 16 bits of the product from the accumulator Latch the upper 16 bits into the PH register ALU status is modified 4 4 2 Class 2 Instructions Accumulator and Constant Reference These instructions provide the ...

Page 121: ...Table 4 17 Class 2a Instruction Description C2a Mnemonic Description 0 0 0 ADDB An imm8 Add an 8 bit positive constant to the accumulator and store the result in the accumulator ALU status is modified 0 0 1 MOVB An imm8 Load an 8 bit positive constant into accumulator ALU status is modified 0 1 0 SUBB An imm8 Subtract 8 bit positive constant from accumulator and store result accumulator ALU status...

Page 122: ...Logical exclusive OR a long constant with accumulator A 0 or 1 Store the result to accumulator A 0 or 1 ALU status is modified 1 1 1 MOV MR imm16 next A Load a long constant to MR in signed mode No change in status 4 4 3 Class 3 Instruction Accumulator Reference These instructions reference the accumulator and in some instances specific registers for transfers Some instructions use a single accumu...

Page 123: ...ster ALU status is modified based on the lookup value 0 0 0 1 1 ZAC An next A ZACS An Zero accumulator A 0 or 1 ALU status is modified 0 0 1 0 0 SUB An An An next A SUB An An An next A SUBS An An An SUBS An An An Subtract offset accumulator from accumulator A 0 or subtract accumulator from offset accumulator A 1 Store the result in accumulator A 0 or 1 ALU status is modified 0 0 1 0 1 ADD An An An...

Page 124: ...roduct high register to accumulator or to offset accumulator and store the result into accumulator A 0 or 1 ALU status is modified The string bit causes an add with carry status CF 0 1 1 1 0 MOV An PH next A MOVS An PH Transfer product high register to accumulator A 0 or offset accumulator A 1 ALU status is modified String bit will cause stringing with current ZF status bit 0 1 1 1 1 EXTSGN An nex...

Page 125: ... or offset accumulator A 0 add lower 16 bits of product to offset accumulator A 1 or accumulator A 0 and store to accumulator A 0 or offset accumulator A 1 Latch upper 16 bits in PH ALU status is modified 1 1 0 1 0 SHLTPL An An next A SHLTPLS An An Barrel shift the accumulator A 1 or 1 value n bits left SV reg Store the upper 16 bits of the 32 bit shift result to PH msbs extended by XM mode bit Tr...

Page 126: ...s transfers to and from memory In indirect mode any one auxiliary register can serve as the address for loading and storing the con tents of another Subclass 4b instructions provide some basic arithmetic operations between referenced auxiliary register and short 8 bit constants from program memory These instructions are included to provide efficient single cycle instructions for loop control and f...

Page 127: ...n Rx 8 bit positive constant into RZF and RCF bits of the STAT register Rx remains unchanged Table 4 24 Class 4c Instruction Description C4c Mnemonic Description 0 0 ADD Rx imm16 Add 16 bit positive constant to Rx register Modify RX status 0 1 SUB Rx imm16 Subtract 16 bit positive constant from Rx register Modify RX status 1 0 MOV Rx imm16 Load Rx with the an 16 bit positive constant Modify RX sta...

Page 128: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 5 1 1 0 1 C5 adrs RET 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 Table 4 27 Class 5 Instruction Description C5 Mnemonic Description 0 0 0 0 0 MOV adrs SV Store SV in the data memory location referred by addressing mode adrs zero filled on upper 12 bits Transfer status is modified 0 0 0 0 1 MOV adrs PH Store the PH in the d...

Page 129: ... adrs Only the lower 8 bits are loaded Transfer status modified 1 0 1 n n MOV APn adrs Load lower 5 bits with content of data memory location referred by addressing mode adrs to accumulator pointer AP register n Transfer status is modified 16 bit value 1 1 0 0 0 MOV MR adrs Load Multiplier MR register with content of data memory location referred by addressing mode adrs and set the multiplier sign...

Page 130: ...heral functions and those that serve external pins For subclass 6b IN and OUT provide bidirectional transfers between the same port address 16 and accumulator In addition IN and OUT instructions in class 6b can communicate with an extra 48 ports a total of 64 including the shared ports Class 6b instructions also have reference to the string bit for checking the arithmetic status of a string transf...

Page 131: ... until another instruc tion that affects them is executed In addition to call a macro call instruction is included This instruction is similar to an unconditional call instruction When executed it pushes the PC 1 value to the STACK and loads a paged vector 7F loaded in the upper 8 bits of PC and an 8 bit vector number loaded into the lower 8 bits of the PC This makes the macro call a single word i...

Page 132: ...itional on ZF 0 and CF 1 0 0 1 0 1 G NG Conditional on SF 0 and ZF 0 0 0 1 1 0 E NE Conditional if ZF 1 and OF 0 0 0 1 1 1 O NO Conditional if OF 1 0 1 0 0 0 RC RNC Conditional on RCF 1 0 1 0 0 1 RA RNA Conditional on RZF 0 and RCF 1 0 1 0 1 0 RE RNE Conditional on RZF 1 0 1 0 1 1 REZI Conditional on value of Rx 0 Not available on Calls 0 1 1 0 0 RLZI Conditional on MSB of Rx 1 Not available on Ca...

Page 133: ...ingle bit decisions and constructing a logical statement through a branch decision tree the program can sequentially combine several status conditions to directly construct a final logic value TF1 or TF2 which can be used to control a subsequent branch or call This class includes two subclasses Class 8a instructions update one of the test flags TF1 or TF2 with a logical combination of the old test...

Page 134: ...from data memory referred by flag addressing mode flagadrs to 0 Table 4 32 SFLAG flagadrs Set flag bit 17th bit from data memory referred by flag addressing mode flagadrs to 1 Table 4 34 Class 8b Instruction Description C8b Mnemonic Description 0 0 MOV TFn cc Rx Load a logic value of the tested condition to one of the test flag bits in status register TF1 or TF2 0 1 OR TFn cc Rx Logically modify o...

Page 135: ...lication between two indirect addressed data memory buffers into a 32 bit accumulator Circular buffer operation Executes in 2 instruction cycles Rx and R x 1 automatically increments by 2 per tap 1 0 CORK An Rx Correlation function When used with repeat will execute 16 16 multiplication between data memory and program memory 48 bit accumulation and a circular buffer operation Each tap takes 3 inst...

Page 136: ...s XM in status register to 0 disabling sign extension mode 1 1 0 0 SFM Sets FM in status register to 1 enabling multiplier shift mode for signed fractional arithmetic 1 1 0 1 RFM Sets FM in status register to 0 enabling multiplier shift mode for unsigned fractional or integer arithmetic 1 1 1 0 SOVM Set OM bit in status register to 1 enabling ALU saturation output DSP mode 1 1 1 1 ROVM Set OM bit ...

Page 137: ... assumed to be zero Instructions that operate on words have internal hardware which increments the byte ad dress appropriately to load the two consecutive bytes in one clock cycle To use an absolute word address the address should be multiplied by 2 A word string is a string of consecutive words Like a byte string word strings use the STR register to define the string length Word strings always st...

Page 138: ...ng Beginning of string at lower address String length times 8 bit data by Incrementing addresses 1 per byte in string Single word Even address if odd address is used the LSB bit of address is assumed 0 16 bit data 2 Word string Even address beginning at a lower address if odd address is used the LSB bit of address is assumed 0 String length times 16 bit data by incrementing addresses 2 per word in...

Page 139: ...C4 0x00BC AC5 0x00DE Example 4 5 5 MOV STR 4 2 MOV AP0 2 MOVS A0 0x0003 Refer to Figure 4 4 for this example The byte string length is 4 AP0 is loaded with 2 and points to AC2 The third instruction loads the value of the string at address 0x0002 LSB bit is assumed 0 and stored into four consecutive accumulators starting from AC2 The result is AC2 0x5678 AC3 0x9ABC AC4 0xDEF0 AC5 0x1122 Same result...

Page 140: ... In the second instruction this flag bit is placed in the TAG status bit of the STAT and the value in RAM location 0x0003 2 is placed in A0 The third instruction resets the flag tag to 0 at the same flag address The fourth instruction reads the same word memory loca tion and writes the TAG bit of STAT which is now 0 Note SFLAG 0x0003 could have been replaced by STAG 0x0003 2 and RFLAG 0x0003 could...

Page 141: ...0x0031 into A0 and also sets the TAG bit of STAT to 1 corre sponding to the last memory location of the string which is word address 0x0032 in this case The next two instructions verify this by setting the flag to zero and reading the memory string again 4 6 MSP50P614 MSP50C614 Computational Modes MSP50P614 MSP50C614 has the following computational modes which are the first 4 bits of the status re...

Page 142: ... Affects OF bit of STAT in case of overflow Fractional SFM RFM STAT FM 1 enables fractional multiplication shift mode The multiplier is shifted left 1 bit to produce a 17 bit operand This mode is used on signed binary fractions and does not require the user to left shift as it would have been required if the FM bit was not set STAT FM 1 turns off fractional mode Sign Extension Mode Sign extension ...

Page 143: ... in unsigned mode The lower 16 bits of the result is stored in A0 and the upper 16 bits are stored in PH The final result is 0x400000 where PH holds the value 0x0040 and A0 holds the lower 16 bits Notice that if the multiplication is not done in unsigned mode the MR is treated as negative We would have obtained 0xFFC00000 PH 0xFFC0 A0 0000 which is the negative value of the previous result The key...

Page 144: ... A0 is loaded with 0x10001000 When the two values are added together it causes an overflow The OF bit of the STAT is set to 1 the 16 bit MSBs of the string become 0x7FFF and the lower bits of the string become 0x2234 The final result is 0x7FFF2234 Note that if overflow mode was not set the result would have been 0x8F002234 Fractional Mode Multiplier fractional mode may be enabled disabled by setti...

Page 145: ... count length N This immediately precedes the instruction to be repeated This next instruction is repeated N 2 times The RPT instruction is useful for clearing RAM locations filtering etc If the repeating instruction utilizes auto increments decrements to either Rx or AC registers i e R2 or A then the repeated modification controls will be permanent If the repeatable instruction is a string instru...

Page 146: ...Interrupts if enabled before the execution of BEGLOOP will automatically be re enabled after exiting the loop Enabling interrupts inside the loop have no effect Queued interrupts are processed according to their priority after the loop exits provided the corresponding interrupt is enabled The loop overhead is 1 instruction cycle per loop cycle ideal for repeating high priority repeated blocks in D...

Page 147: ...atus is modified representing the outcome of the entire operation Examine the following examples Table 4 43 Initial Processor State for String Instructions Registers register value AP0 2 AP1 21 0x15 AP2 11 0x0B AP3 29 0x1D AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 0xAAAA AC12 0xAAAA AC13 0xAAAA AC14 0xAAAA AC15 0xAAAA AC16 AC17 AC18 AC19 AC20 AC21 0x1223 AC22 0xFBCA AC23 0x233E data memory...

Page 148: ...sequence ends with ADDS or SUBS used with PH 6 These sequences may not give same result when single step debugging because single stepping changes the internal state They should be used either with a hardware breakpoint or with fast run mode The breakpoint should be set after the sequence ends For example MULAPL A0 A0 ADDS A0 A0 PH The first instruction performs a multiply accumulate with MR and A...

Page 149: ...e adrs The string length is defined in STR register MOVS An An The program memory string address is stored in accumulator An or its offset An Store the contents of this address to the accumulator string An or its offset An The string length is defined in STR register Data Manipulation on Strings ADDS An An pma16 ADD the accumulator string An or its offset An with the program memory string at locat...

Page 150: ...efficient data see section 4 10 any interrupt occurring between loading the first coefficient and the execution of a FIRK CORK will change the last value of DP if the interrupt routine uses a lookup instruction DP can be stored in RAM MOV adrs DP and a restoration is done as follows MOV An adrs SUB An 0x1 MOV An An Context save and restore of instructions are not required if filter instructions ar...

Page 151: ...he OUT instruction Class 6 The OUT instruction can specify a memory address and a 4 bit port address It can also use an accumulator or offset accumulator and a 6 bit port address String transfers are allowed between the accumulators and the output port 4 11 Special Filter Instructions The MSP50P614 MSP50C614 processor can perform some DSP functions Fundamental to many filtering algorithms is the F...

Page 152: ... bit extended accumulate cycle is added to prevent the arithmetic overflow common in auto correlation filters FIR COR instructions The execution of the filter instructions is shown in Figure 4 6 To use FIR COR instructions some initial setup is required ConsecutiveRxpair Rxeven Rxeven 1 shouldbechosenwithRxevenpointing to the RAM sample buffer array and Rxeven 1 pointing to the RAM coefficient arr...

Page 153: ... Second initialize filter coeffs to proper values NOTE In this code N must be less than 33 since there are only 32 accumulator registers mov STR N 2 set string length to N zacs a0 zero out N accumulators mov a0 FIR_COEFFS point to filter coeffs movs a0 a0 get N filter coeffs mov r0 coeffs point to RAM locs for filter coeffs movs r0 a0 put filter coeffs into RAM locs mov a0 circBuff set up pointer ...

Page 154: ...fer Thus R0 will increment by R5 after the first multiply This will become more clear after examining the next ex ample code The third detail is that the filter coefficients take up only N RAM locations but the circular buffer takes up N 1 RAM locations Below is an example of the FIR or COR execution inside a DAC interrupt ser vice routine FIR Filtering routine N 3 rovm reset overflow mode mov R5 ...

Page 155: ...ppose a four word circular buffer starts at RAM location 0x0100 and ends at 0x0106 N 3 In order to wrap around from location 0x0106 back to location 0x0100 the value 0x006 must be subtracted from 0x0106 giving 0x0100 0x0100 TAGGED LOCATION 0x0106 0x0104 0x0102 Go back N words to wrap around R0 must point to the current starting point of the circular buffer R1 must point to the filter coefficients ...

Page 156: ...ering operation in the example is located in AC0 lower word and AC1 high word This 32 bit result is stored in the SampleOut RAM location R0 should be pointing to the oldest sample The oldest sample x k 3 is overwritten by the next sample to be filtered x k 1 R0 is saved in the startOfBuff pointer for the next FIR COR instruction Notice that R0 points backwards by one location from its starting poi...

Page 157: ...wing code rovm reset overflow mode mov R5 2 N circular buffer length 3 words mov A0 FIRK_COEFFS Loads address of lookup table mov A0 A0 Loads first coefficient to A0 and sets DP mov MR A0 Load first coefficient in to MR register In the sequence of code above the DP register points to the first filter coeffi cient in program memory located at FIRK_COEFFS This happens during the mov A0 A0 instructio...

Page 158: ...n AC0 16 32 in AC1 mov A0 nextSample Replace last sample with newest sample and update mov R0 A0 the start of the mov startOfBuff R0 circular buffer to here R0 The set up for the FIRK CORK instruction is the same as the set up for the FIR COR instruction with the exception that the filter coefficients do not need to be loaded into RAM locations Rather they can be included just before speech data o...

Page 159: ...k 0 N Data memory FIR COR Program memory FIRK CORK sample_buf coeff_array ACr 1 ACr 2 ACr y For COR CORK ACr ACr 1 y For FIR FIRK TAG 1 for 2nd to last sample for Circular buffer operation Accumulators Pointer Point to accumulator ACr An ACn Circular buffer operation only Circular buffer length 2N R5 sample_buf address Rxeven R0 R2 R4 R6 coeff_array address DP coeff_array address Rxeven 1 R1 R3 R5...

Page 160: ...0 0 h 3 h 4 0 0 0 h N 1 0 0 0 h N 0 0 16 Bits 17th Bit coeff_array coeff_array is stored in program or data memory based on filter instruction x k x k 1 x k 2 0 0 0 x k 3 x k 4 0 0 0 x k N 0 0 1 x k 1 0 16 Bits 17th Bit sample_buf x x x x x x x STAT x k N 1 is replaced by x k 1 y Σk 0 N h m x k m R5 2 N 1 program memory FIRK CORK data memory FIR COR 48 bit accumulation for COR CORK 32 bit accumula...

Page 161: ...CF ZF 0 CF 0 Below unsigned B NAE NB AE ZF 0 CF 1 Above unsigned A NBE NA BE ZF 1 SF 0 Greater signed G NLE NG LE ZF 1 OF 0 Equal E NE OF 1 Overflow flag OF NOF ZF 0 SF 1 Less signed L NGE NL GE RCF 1 Rx carry flag RCF RNCF RZF 0 RCF 1 Rx above unsigned RA RNBE RNA RBE RZF 1 Rx equal RE RZ RNE RNZ TF1 1 Test flag 1 TF1 NTF1 TF2 1 Test flag 2 TF2 NTF2 TAG 1 Memory tag TAG NTAG IN1 Input line 1 IN1 ...

Page 162: ...d Post modification of a register This can be either next A or Rmod and will be specified in the instruction The following table describes the meanings of the symbols used in the instruction set descriptions Bold type means it must be typed exactly as shown italics type means it is a variable square brackets enclose optional arguments Operands 0 dma6 63 0 dma16 65535 dma16 639 for MSP50P614 MSP50C...

Page 163: ... the addressed memory and the upper bits may not be used If n is not provided data width is 16 bits cc Condition code bits used with conditional branch calls and test flag bit instructions cc Conditional code mnemonic used with conditional branch calls and test flag bit instructions Curly braces indicates this field is not optional CF Carry flag clk Total clock cycles per instruction dma n n bit d...

Page 164: ...igh register 16 bits PL Product low register 16 bits cannot be read written directly R Rx register treated as a general purpose register This bit is not related to any addressing mode RCF Register carry flag Rx Indirect register x where x 0 7 RZF Register zero flag s Represents string mode if 1 otherwise normal mode SF Sign flag STAT Status register 17 bits STR String register 8 bits SV Shift valu...

Page 165: ... 0 0 x 0 0 Short relative 1 1 nR 2 R6 offset7 1 offset7 Relative to R5 1 1 nR 2 Rx R5 0 1 0 Rx 0 0 Long relative 2 2 nR 4 Rx offset16 0 0 1 Rx 0 0 Rx 0 0 Indirect 1 1 nR 2 Rx 0 1 Indirect 1 1 nR 2 Rx 0 1 1 Rx 1 0 Rx R5 1 1 Replace nR with nS for string operation Note dma16 and offset16 is the second word Table 4 47 Flag Addressing Syntax and BIts Repeat flagadrs flag addressing mode encoding flaga...

Page 166: ...d the legend in Section 4 13 to help with individual instruction descriptions Each instruction is discussed in detail and provides the following information Assembler syntax Clock cycles required with or without repeat instructions Words required Limitation and restrictions Execution Affected flags Opcode Description Recommendation to other related instructions See Also field Examples ...

Page 167: ...c for two operands dest src src1 for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly src1 is adrs TAG is set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD An An adrs next A 0 0 0 0 A next A An adrs x dma16 for direct or offset16 long relative see section 4 13 ADD An An imm16 next A 1 1 1 0 0 next...

Page 168: ...put result in A2 Add value in R5 to R2 and store in R2 Example 4 14 1 2 ADD A1 A1 0x1221 Add immediate value of 0x1221 to A1 and store result in A1 Example 4 14 1 3 ADD A0 A0 PH Add PH to accumulator A0 and store result in accumulator A0 Example 4 14 1 4 ADD A1 A1 A1 Add accumulator A1 to accumulator A1 put result in accumulator A1 Example 4 14 1 5 ADD R3 0x1000 Add 0x1000 to register R3 store res...

Page 169: ...are set accordingly dest is Rx RCF RZF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDB An imm5 1 0 1 0 0 0 0 An imm8 ADD Rx imm8 1 0 1 1 0 0 k4 k3 k2 k7 k6 k5 Rx k1 k0 See Also ADD ADDS SUB SUBB SUBS Description Add immediate value of unsigned src byte to value stored in dest register and store result in the same dest register Example 4 14 2 1 ADDB A2 0x45 Add...

Page 170: ... this instruction An in this instruc tion should be the same as An in one of the listed class 1b instruction Offsets are allowed See Section 4 8 for more detail Execution dest string src string src1 string PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly src1 is adrs TAG is set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDS An An adrs 0 0 0 0 A 1 1 A...

Page 171: ...on multiplies MR and A0 adds PL to A0 and stores the result in A0 The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0 Note that MULAPL and ADDS constitute a special sequence When this sequence occurs interrupts are NOT disabled so interrupts should be disabled for correct operation In extended sign mode if A0 is AC0 0x0000 A0 is AC16 0...

Page 172: ...ma16 for direct or offset16 long relative see section 4 13 AND An An imm16 next A 1 1 1 0 0 next A An 1 0 1 0 0 1 A A x imm16 AND An An An next A 1 1 1 0 0 next A An 0 1 0 1 0 0 A A AND TFn flagadrs 1 0 0 1 1 flg Not 1 0 0 flagadrs AND TFn cc Rx 1 0 0 1 0 flg Not cc Rx 1 0 Description Syntax Description AND dest src src1 mod Bitwise AND src1 and src and store result in dest Premodification of accu...

Page 173: ...ample 4 14 4 2 AND A0 A0 0xff0f A Predecrement accumulator pointer AP0 And immediate value 0xff0f to register accumulator A0 store result in accumulator A0 Example 4 14 4 3 AND TF2 0x0020 AND global flag bit at RAM word location 0x0020 to TF2 in the STAT Store result in the TF2 bit in the STAT register Note that flagadrs cannot exceed values greater than 0x003F Example 4 14 4 4 AND TF1 TF2 AND TF1...

Page 174: ...cted OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANDB An imm8 1 0 1 0 1 0 1 An imm8 Description Bitwise AND src byte and byte stored in dest register and store result in dest register See Also AND ANDS OR ORB ORS XOR XORB XORS Example 4 14 5 1 ANDB A2 0x45 AND immediate value 0x45 to A2 byte mode Store result in A2 Upper 8 bits of A2 will be ANDed w...

Page 175: ...et16 long relative see section 4 13 ANDS An An pma16 1 1 1 0 0 1 1 An 1 0 1 0 0 1 A A x pma16 ANDS An An An 1 1 1 0 0 1 1 An 0 1 0 1 0 0 A A Description Syntax Description ANDS dest src Bitwise AND of src string and dest string and store result in dest string ANDS dest src src1 Bitwise AND src1 string src string and store result in dest string See Also AND ANDB OR ORB ORS XOR XORB XORS Example 4 1...

Page 176: ... are actually queued until the loop is complete see ENDLOOP The loop executes N number of times Thus N 2 should be loaded in R4 in order to loop N times BEGLOOP and ENDLOOP block has following restrictions No CALL instructions can be used All maskable interrupts are queued BEGLOOP ENDLOOP block cannot be nested See Also ENDLOOP Example 4 14 7 1 MOV R4 count 2 init R4 with loop count BEGLOOP ADD A0...

Page 177: ...1 0 0 0 1 1 0 An 0 0 0 0 0 0 0 0 Description PC w is pushed onto the top of stack TOS and the second word operand or accumulator value is loaded into the PC Call instructions cannot immedi ately followed by RET instructions No restrictions apply if IRET is used instead of RET Syntax Description CALL pma16 Unconditional call to specified program memory address pma16 CALL An Call to address referenc...

Page 178: ...ma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 label label label label label label label label label label label label label label label label label label label label CNZ CNS CNC CNG CNE CNA CNB CNO CRNC CRNE CNL CNTF1 CNTF2 CNTAG CNIN1 CNIN2 CXNZ CXNS CXNG CRNA pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16...

Page 179: ... 1 0 1 0 RE RNE Conditional on RZF 1 Not condition RZF 0 0 1 0 1 1 RZP RNZP Conditional on value of Rx 0 Not available on Calls Not condition Rx 0 0 1 1 0 0 RLZP RNLZP Conditional on MSB of Rx 1 Not available on Calls Not condition MSB of Rx 0 0 1 1 0 1 L NL Conditional on ZF 0 and SF 1 Not condition ZF 0 or SF 1 0 1 1 1 0 Reserved 0 1 1 1 1 Reserved 1 0 0 0 0 TF1 NTF1 Conditional on TF1 1 Not con...

Page 180: ...al CG pma16 CNG pma16 CNLE pma16 CLE pma16 Conditional call on greater signed Conditional call on not greater signed CIN1 pma16 CNIN1 pma16 Conditional call on IN1 1 Conditional call on IN1 0 CIN2 pma16 CNIN2 pma16 Conditional call on IN2 1 Conditional call on IN2 0 CL pma16 CNL pma16 CNGE pma16 CGE pma16 Conditional call on less signed Conditional call on not less signed CO pma16 CNO pma16 Condit...

Page 181: ...0 Alternate mnemonics are provided as a way of improving source code readability They generate the same opcode as the original mnemonic For example CA call above tests the same conditions as CNBE call not below or equal but may have more meaning in a specific section of code See Also CALL VCALL RET IRET Example 4 14 9 1 CZ 0x2010 Call routine at program memory address 0x2010 if a previous operatio...

Page 182: ...dma16 for direct or offset16 long relative see section 4 13 CMP An imm16 next A 1 1 1 0 0 next A An 0 1 1 0 0 1 A A x imm16 CMP An An next A 1 1 1 0 0 next A An 1 0 0 0 0 0 0 0 CMP An An next A 1 1 1 0 0 next A An 1 0 0 0 0 0 1 0 CMP Rx imm16 1 1 1 1 1 1 1 0 0 0 1 1 Rx 0 0 x imm16 CMP Rx R5 1 1 1 1 1 1 1 0 0 1 1 1 Rx 0 0 Description Subtract value of src1 from src i e src src1 and only modify the ...

Page 183: ...1 Assembly Language Instructions Example 4 14 10 3 CMP R2 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly Example 4 14 10 4 CMP R0 R5 Compare value at R0 to R5 and change the STAT flags accordingly ...

Page 184: ...is Rx RCF RZF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMPB An imm8 1 0 1 0 0 1 1 An imm8 CMPB Rx imm8 1 0 1 1 1 1 k4 k3 k2 k7 k6 k5 Rx k1 k0 Description Subtract value of src1 zero filled in upper 8 bits from src i e src src1 and only modify the status flags Contents of src not changed See Also CMP CMPS Jcc Ccc Example 4 14 11 1 CMPB A0 0xf3 Compare immedia...

Page 185: ...a16 for direct or offset16 long relative see section 4 13 CMPS An pma16 1 1 1 0 0 1 1 An 0 1 1 0 0 1 A 0 x pma16 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 0 0 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 1 0 Description Subtract src1 string from src string and only modify the status flags Content of accumulators are not changed See Also CMPB CMP Jcc Ccc Example 4 14 12 1 CMPS A0 R0 Compare string at data...

Page 186: ...d in section 4 11 Flags Affected none Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COR An Rx 1 1 1 0 1 0 0 An 1 1 0 Rx 1 1 Description When used with repeat will execute 16 16 multiplication between two indirectly addressed data memory buffers 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles The selected register Rx must be even This instructi...

Page 187: ...1 k Execution is detailed in section 4 11 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CORK An Rx 1 1 1 0 1 0 0 An 1 0 0 Rx 1 1 Description When used with repeat will execute 16 16 multiplication between data memory and program memory 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles Selected register Rx must be even This in...

Page 188: ...arks the end of a loop defined by BEGLOOP If register R4 is not negative R4 is decremented by n and the loop is executed again beginning with the first instruction after the BEGLOOP If R4 is negative a NOP instruction is executed and program exits the loop Interrupts queued by BEGLOOP are processed according to their priority This instruction results in an overhead of one instruction cycle per loo...

Page 189: ...ecution premodify AP if mod specified new most significant word of dest STAT SF PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTSGN An next A 1 1 1 0 0 next A An 0 1 1 1 1 0 0 A Description Copy accumulator sign flag SF to all 16 bits of An See Also EXTSGNS Example 4 14 16 1 EXTSGN A0 A Preincrement accumulator pointer AP0 Sign extend the accumulator A0 ...

Page 190: ...stall when an attempt is made to sign extend a string that has all zeros in it Also the same interrupt problem on the accumulator pointers exists if the instruction just before is not a string instruction For customers who need the EXTSGNS function now as it was originally intended for string data there is a workaround Unfortunately it involves the use of two accumulator pointers the second pointi...

Page 191: ...code MOV AP0 0 POINT TO LSW OF ACCUM STRING MOV AP1 3 Point to loc corresponding to extended word in acc ZAC A1 INITIALIZE EXTENDED SIGN VALUE as positive MOVS A0 R0 R0 POINTS TO VALUE IN MEMORY JNS POSITIVE branch around negative extension accepting default pos extension NOT A1 INVERT EXTENDED SIGN WORD FOR NEG CASE POSITIVE See Also EXTSGN Example 4 14 17 1 EXTSGNS A0 Sign extend accumulator str...

Page 192: ...e Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIR An Rx 1 1 1 0 1 0 0 An 0 1 0 Rx 1 1 Description Finite impulse response FIR filter Execute finite impulse response filter taps using coefficients from data memory and samples from data memory The instruction specifies two registers Rx and R x 1 which sequentially address coefficients and the sample buffer in the two instruction FIR...

Page 193: ...1 Assembly Language Instructions See Also RPT FIRK COR CORK Example 4 14 18 1 RPT 0 FIR A0 R0 Computes the calculation for 2 tap FIR filter with 32 bit accumulation See section 4 11 for more detail on the setup of coefficients and sample data ...

Page 194: ...0 0 0 Rx 1 1 Description Finite impluse response FIR filter Execute finite impulse response filter taps using coefficients from program memory and samples from data memory Address reference for data memory is indirect using specified Rx and address reference for program memory is contained in DP register This instruction must be used with RPT instruction When used with the repeat counter it will e...

Page 195: ...ster Example 4 14 20 1 MOV A0 0 OUT 0x34 A0 Turn off DAC MOV A0 0x0400 Turn off clock idle bit 1 OUT 0x3d A0 Write in ClkSpdCtrl write only IN A0 0x38 Read IntGenCtrl register value OR A0 A0 0x4000 Set ARM 1 OUT 0x38 A0 Write to IntGenCtrl IDLE Go to deep sleep mode To understand this routine refer to the Reduced Power Modes table in section 2 11 The bits to be set up to switch to deep sleep mode ...

Page 196: ...s 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IN adrs port4 1 1 0 0 0 port4 adrs x dma16 for direct or offset16 long relative see section 4 13 IN An port6 1 1 1 0 1 1 0 An port6 A Description Input from I O port Words can be input to memory from one of 16 port addresses or one of 48 port addresses The port4 address is multiplied by 4 to get the actual port address See Also INS OUT OUTS Example 4 14 2...

Page 197: ...ns 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INS An port6 1 1 1 0 1 1 1 An port6 0 A Description Input string from same port port6 to accumulator string Strings can be input to accumulators from one of 64 port addresses In this instruction port6 is sampled nS 2 times The first sample is stored in the lowest order accumula tor of the string and the last sample is stored in the highest order accumula...

Page 198: ...d None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTD 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 Description Disables interrupts Resets bit 4 the IM interrupt mask bit of status register STAT to 0 See Also INTE IRET Example 4 14 23 1 INTD Disable interrupts INTD must be always be immediately followed by a NOP Any maskable interrupt occurring after the INTD NOP sequence will not be servic...

Page 199: ...tion STAT IM 1 IM is STAT bit 4 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTE 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 Description Enables interrupts Sets bit 4 the IM interrupt mask bit of status register STAT to 1 See Also INTD IRET Example 4 1 INTE Enables interrupts Any maskable interrupts occurring after this instruction is serviced ...

Page 200: ...on PC TOS R7 R7 2 TOS R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 See Also RET CALL Ccc INTE INTD Description Return from interrupt Pop top of stack to program counter Example 4 1 IRET Return from interrupt service routine If used in a called subroutine return from subroutine ...

Page 201: ...Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod label label label label label label label label label label label label label label label label label label label label label label JNZ JNS JC JNG JNE JNA JNB JNO JRNC JRNE JNL JNTF1 JNTF2 JNTAG JNIN1 JNIN2 JXNZ JXNS JXNG JRNA JRNZP JRNLZP pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod p...

Page 202: ... if OF 1 Not condition OF 0 0 1 0 0 0 RC RNC Conditional on RCF 1 Not condition RCF 0 0 1 0 0 1 RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCF 1 0 1 0 1 0 RE RNE Conditional on RZF 1 Not condition RZF 0 0 1 0 1 1 RZP RNZP Conditional on value of Rx 0 Not condition Rx 0 0 1 1 0 0 RLZP RNLZP Conditional on MSB of Rx 1 Not condition MSB of Rx 0 0 1 1 0 1 L NL Conditional on ZF 0 and...

Page 203: ...itional jump on not equal JG pma16 Rmod JNLE Conditional jump on greater signed JNG pma16 Rmod JLE Conditional jump on not greater signed JIN1 pma16 Rmod Conditional jump on port D pin PD0 1 JNIN1 pma16 Rmod Conditional jump on port D pin PD0 0 JIN2 pma16 Rmod Conditional jump on port D pin PD1 1 JNIN2 pma16 Rmod Conditional jump on port D pin PD1 0 JL pma16 Rmod JNGE Conditional jump on less than...

Page 204: ...ansfer ZF 1 zero JXNZ pma16 Rmod Conditional jump on transfer ZF 0 not equal JZ pma16 Rmod Conditional jump on ZF 1 JNZ pma16 Rmod Conditional jump on ZF 0 Alternate mnemonics are provided as a way of improving source code readability They generate the same opcode as the original mnemonic For example JA jump above tests the same conditions as JNBE jump not below or equal but may have more meaning ...

Page 205: ... 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 x pma16 JMP pma16 Rx 1 0 0 0 0 0 0 1 0 1 0 1 Rx 0 1 x pma16 JMP pma16 Rx 1 0 0 0 0 0 0 1 0 1 0 1 Rx 1 0 x pma16 JMP pma16 Rx R5 1 0 0 0 0 0 0 1 0 1 0 1 Rx 1 1 x pma16 JMP An 1 0 0 0 1 0 0 An 0 0 0 0 0 0 0 0 Description Instruction Operation JMP pma16 mod PC is replaced with second word operand Post modification of Rx register is done if specified JMP An PC is rep...

Page 206: ...3 MOV adrs Rx Table 4 46 Table 4 46 4a MOV Rx adrs Table 4 46 Table 4 46 4a MOV Rx imm16 2 2 N R 4c MOV Rx R5 1 1 nR 3 4d MOV SV adrs 4 1 1 nR 3 5 MOV PH adrs Table 4 46 Table 4 46 5 MOV MR adrs Table 4 46 Table 4 46 5 MOV APn adrs Table 4 46 Table 4 46 5 MOV STAT adrs Table 4 46 Table 4 46 5 MOV TOS adrs Table 4 46 Table 4 46 5 MOV adrs PH Table 4 46 Table 4 46 5 MOV adrs MR Table 4 46 Table 4 46...

Page 207: ...n adrs next A 0 0 1 0 A next A An adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs An 0 1 0 1 1 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOV An imm16 next A 1 1 1 0 0 next A An 0 0 1 0 0 1 0 A x imm16 MOV MR imm16 next A 1 1 1 0 0 next A An 1 1 1 0 0 1 0 0 x imm16 MOV An An next A 1 1 1 0 0 next A An 0 0 1 1 1 0 A A MOV An PH next A 1 1 1...

Page 208: ...6 long relative see section 4 13 MOV adrs MR 1 1 0 1 0 1 0 0 0 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs STAT 1 1 0 1 0 0 0 1 0 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs STR 1 1 0 1 0 0 0 1 1 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs DP 1 1 0 1 0 1 0 1 0 adrs x dma16 for direct or offset16 long re...

Page 209: ...ct high PH register MOV MR adrs Move data memory word to MR set multiplier signed mode MOV adrs An Move ROM word at An to data memory MOV APn adrs Move data memory word lower 6 bits to APn register MOV STAT adrs Move data memory word to status register STAT MOV SV adrs Move data memory value lower 4 bits to shift value SV register MOV TOS adrs Move data memory word to top of stack TOS MOV adrs PH ...

Page 210: ...ple 4 14 28 3 MOV 0x0200 2 A1 Transfer content of program memory location pointed by A1 to word data memory location 0x0200 Example 4 14 28 4 MOV A2 0xf200 A Predecrement accumulator pointer AP2 Load accumulator A2 with immediate value 0xf200 Example 4 14 28 5 MOV A0 A0 Copy content of accumulator A0 to accumulator A0 Example 4 14 28 6 MOV A0 A0 Copy content of accumulator A0 to accumulator A0 Exa...

Page 211: ...a memory location stored in R3 to accumulator pointer AP2 Example 4 14 28 18 MOV R6 8 2 DP Copy data pointer DP to data memory word location pointed by R6 offset by 8 location short relative addressing Example 4 14 28 19 MOV STR 0x0200 2 Copy the STR register with the content of word memory location 0x0200 Example 4 14 28 20 MOV R6 0x20 TF2 Copy TF2 flag to the flag bit in relative flag location R...

Page 212: ...gly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVAPH An MR adrs 0 1 1 0 1 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR register add PH to An in parallel See Also MOVAPHS MOVTPH MOVTPHS MOVSPH MOVSPHS Example 4 14 34 1 MOVAPH A0 MR R3 R5 Load the contents of the byte address created by adding R3 and R5 to the MR registe...

Page 213: ... 2 1 0 MOVAPHS An MR adrs 0 1 1 0 1 0 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR add PH to second word in An string Certain restriction applies to the use of this instruction when interrupts are occuring on the background See section 4 8 for more details See Also MOVAPH MOVTPH MOVTPHS MOVSPH MOVSPHS Example 4 14 35 1 MOVAPHS A0 MR R3 R5 ...

Page 214: ...rs 0 1 0 0 1 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVB adrs An 0 1 0 1 0 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVB An imm8 1 0 1 0 0 0 1 An imm8 MOVB MR imm8 1 0 1 0 1 1 1 An imm8 MOVB Rx imm8 1 0 1 1 1 0 k4 k3 k2 k7 k6 k5 Rx k1 k0 Description Copy value of unsigned src byte to dest byte Syntax Description MOVB An adrs Move ...

Page 215: ...A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2 Example 4 14 29 3 MOVB A0 0xf2 Load accumulator A0 with value of 0xf2 Example 4 14 29 4 MOVB MR 34 Load MR register with immidiate value of 34 decimal Example 4 14 29 5 MOVB R2 255 Load R2 with immidiate value of 255 decimal ...

Page 216: ...1 10 9 8 7 6 5 4 3 2 1 0 MOVBS An adrs 8 0 1 0 0 1 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVBS adrs 8 An 0 1 0 1 0 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Copy value of src byte to dest Syntax Description MOVBS An adrs Move data memory byte string to An word string MOVB adrs An Move An byte string to data memory See ...

Page 217: ...s An OF SF ZF CF are set accordingly dest is adrs XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVS An adrs 0 0 1 0 A 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVS adrs An 0 0 0 1 A 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVS adrs An 0 1 0 1 1 1 1 A...

Page 218: ... as if the sequence was a single string MOVS An An Move program memory string at An to An See Also MOVU MOV MOVT MOVB MOVBS Example 4 14 31 1 MOVS A2 R6 Load the string pointed by R6 to accumulator string A2 Example 4 14 31 2 MOVS R4 A2 Copy the accumulator string A2 to data memory location pointed by R4 Example 4 14 31 3 MOVS 0x0100 2 A0 Transfer the program memory word string pointed by content ...

Page 219: ...ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVSPH An MR adrs 0 1 1 0 0 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move data memory to MR subtract PH from An store result in An See Also MOVSPHS MOVAPH MOVAPHS MOVTPH MOVTPHS Example 4 14 36 1 MOVSPH A0 MR R3 R5 Load the content of byte address created by adding R3...

Page 220: ...MR adrs 0 1 1 0 0 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move data memory word string to MR subtract PH from second word An string Store result in An Certain restrictions apply to the use of this instruction when interrupts are occuring on the background See Section 4 8 for more details See Also MOVSPH MOVAPH MOVAPHS MOVTPH MOVTPHS Example 4 14 37 1 M...

Page 221: ...st src PC PC w Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVT adrs TFn 1 1 0 1 0 1 1 1 fig adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move TFn from STAT register to memory tag All addressing modes are available See Also MOVU MOV MOVT MOVB MOVBS MOVS Example 4 14 32 1 MOVT R3 TF2 Copy the TF2 flag bit to the 17th bit of the ...

Page 222: ... 1 0 0 next A An 1 0 1 1 1 0 A 0 MOVU MR adrs 1 1 0 1 1 1 0 0 1 adrs x dma16 for direct or offset16 long relative see section 4 13 Description Copy value of src to dest Premodification of accumulator pointers is allowed with some operand types Syntax Description MOVU MR An next A Move An to MR register in unsigned multiplier mode MOVU MR adrs Move data memory word to MR reset multiplier signed mod...

Page 223: ... Instructions Figure 4 8 Valid Moves Transfer in MSP50P614 MSP50C614 Instruction Set PH An Rx APn STR MR SV Immediate B B B S B S S B ROM RAM S I O xxxxxx xxxx00 STAT TOS B Flag Bit NOTE B Byte move possible S String move possible R5 can be moved to Rx An to An ...

Page 224: ...nd src The 16 MSBs of the 32 bit product are stored in the the PH register The contents of the accumulator are not changed The upper 16 bits of the result are rounded for MUL An but not for MUL adrs Pre modify the accumulator pointer if specified Syntax Description MUL An next A Multiply MR by An word store result in An MUL adrs Multiply MR by data memory word Round upper 16 bits No status change ...

Page 225: ... 4 3 2 1 0 MULS An 1 1 1 0 0 1 1 An 1 1 1 1 0 0 A 0 Description Multiply MR and the value in src The 16 MSBs of the ns 3 x 16 bit product are stored in the PH register The value in src is unchanged and the value in PL is ignored This instruction rounds the upper 16 bits Note that An is a string of length nS 2 where nS is the value in STR register See Also MUL MULR MULAPL MULSPL MULSPLS MULTPL MULT...

Page 226: ...on of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest Certain restriction applies to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more detail Syntax Description MULAPL adrs Multiply MR by RAM word add PL t...

Page 227: ...n 1 1 0 0 1 0 A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ns 3 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest string Syntax Description MULAPLS adrs Multiply MR by RAM string add PL to An MULAPLS An An next A Multiply MR by An string add PL to An See Also ...

Page 228: ...egister MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register are subtracted from dest Certain restrictions apply to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more details Syntax Description MULSPL adrs Multiply MR by RAM word substract PL ...

Page 229: ... 1 An 1 1 0 0 0 0 A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ns 3 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register subtracted from dest string Syntax Description MULSPLS adrs Multiply MR by data memory string subtract PL from An MULSPLS An An Multiply MR by An string sub...

Page 230: ... 0 1 1 0 A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register are stored in An Certain restrictions apply to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more detail Syntax Descripti...

Page 231: ...on 4 13 MULSPL S An An 1 1 1 0 0 1 1 An 1 1 0 1 1 0 A A Description Perform multiplication of multiply register MR and value of src string The 16 MSBs of the ns 3 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register stored in An string Syntax Description MULTPLS An adrs Multiply MR by effective data memory string move PL to An MU...

Page 232: ...C 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEGAC An An next A 1 1 1 0 0 next A An 0 0 0 0 0 0 A A Description Perform two s complement negation of src accumulator and store result in dest accumulator See Also NEGACS SUB SUBB SUBS ADD ADDB ADDS NOTAC NOTACS Example 4 14 46 1 NEGAC A3 A3 A Predecrement accumulator pointer AP3 Negat...

Page 233: ... src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MULSPL S An An 1 1 1 0 0 1 1 An 0 0 0 0 0 0 A A Description Perform two s complement negation of src accumulator string and store result in dest accumulator string See Also NEGAC SUB SUBB SUBS ADD ADDB ADDS NOTAC NOTACS Example 4 14 47 1 NEGACS A3 A3 Negate accumulator string A3...

Page 234: ...R 3 9d Execution PC PC 1 No operation Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description This instruction performs no operation It consumes 1 clock of execution time and 1 word of program memory See Also RPT Example 4 14 48 1 NOP Consumes 1 clock cycle ...

Page 235: ...ed OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTAC An An next A 1 1 1 0 0 next A An 0 0 0 0 1 0 A A Description Premodify accumulator pointer if specified Perform one s complement of src accumulator and store result in dest accumulator See Also NOTACS AND ANDB ANDS OR ORB ORS XOR XORB XORS NEGAC NEGACS Example 4 14 49 1 NOTAC A3 A3 A Predecrement ...

Page 236: ...F ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTACS An An 1 1 1 0 0 1 1 An 0 0 0 0 1 0 A A Description Perform one s complement of src accumulator string and store result in dest accumulator string See Also NOTAC AND ANDB ANDS OR ORB ORS XOR XORB XORS NEGAC NEGACS Example 4 14 50 1 NOTACS A3 A3 Take the one s complement invert bits of the accumulator str...

Page 237: ...ma16 for direct or offset16 long relative see section 4 13 OR An An imm16 next A 1 1 1 0 0 next A An 1 0 0 0 0 1 A A OR An An An next A 1 1 1 0 0 next A An 0 1 0 0 1 0 A A OR TFn flagadrs 1 0 0 1 1 fig Not 0 1 0 flagadrs OR TFn cc Rx 1 0 0 1 0 fig Not cc Rx 0 1 Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src and src1 store result ...

Page 238: ... OR A1 A1 A1 A Pre decrement accumulator pointer AP1 OR accumulator A1 to accumulator A1 put result in A1 Example 4 14 51 4 OR TF1 R6 0x22 OR TF1 bit in STAT with tag bit 17th bit at relative flag address 0x22 relative to R6 i e R6 0x22 store result in TF1 flag in STAT Example 4 14 51 5 OR TF1 ZF OR ZF flag in STAT register with to TF1 put result in TF1 bit in STAT Example 4 14 51 6 OR TF2 RZP R2 ...

Page 239: ... dest OR src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ORB An imm8 1 0 1 0 1 0 0 An imm8 Description Bitwise OR byte of src and dest Result is stored in dest Only lower 8 bits of accumulator is affected See Also OR ORS AND ANDS XOR XORS NOTAC NOTACS Example 4 14 52 1 ORB A2 0x45 OR 0x45 immediate to accumulator A2 lower 8 bi...

Page 240: ...0 1 0 A A Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src1 and src store result in dest Syntax Description ORS An adrs OR RAM string to An string ORS An An pma16 OR ROM string to An string store result in An string ORS An An An OR An string to An string store result in An string See Also OR ORB AND ANDS XOR XORS NOTAC NOTACS Examp...

Page 241: ...4 adrs 1 1 0 0 1 port4 adrs x dma16 for direct or offset16 long relative see section 4 13 OUT port6 An 1 1 1 0 1 1 0 An port6 1 A Description Output to I O port Words 16 bits in memory can be output to one of 16 port addresses Words 16 bits in the accumulators can be output to these same 16 port addresses or to an additional 48 port addresses Note that port4 address is multipled by 4 to get the ac...

Page 242: ...10 9 8 7 6 5 4 3 2 1 0 OUTS port6 An 1 1 1 0 1 1 1 An port6 1 A Description Output to I O port Word in the accumulator string can be output to one of 64 port addresses String operation writes several consecutive ports starting from port6 specified in the instruction See Also OUT IN INS Example 4 14 55 1 OUTS 0x04 A3 Put the content of acccumulator string A3 to I O port string address 0x04 PADIR po...

Page 243: ...tion Return from call or vectored call Pop stack to program counter continue execution Returns from subroutine calls CALL Ccc instructions and interrupts are different because of the way each process is handled In order to prevent execution pipeline problems the interrupt return IRET instruction uses two cycles and the Return RET instruction cannot immediately follow a CALL i e RET followed by a R...

Page 244: ...s two groups of memory flag addresses global flags which are the first 64 word locations in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only addresses the 17th bit See section 4 3 7 for more information See Also SFLAG STAG RTAG Example 4 14 57 1 RFLAG 0x21 Resets the flag bit at RAM byte location 0x0042 to zero Example 4 14 57 2 RFLAG R6 0x0...

Page 245: ...Execution STAT FM 0 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets fractional mode Clears bit 3 in status register STAT Disable multiplier shift mode for unsigned fractional or integer arithmetic See Also SFM Example 4 14 58 1 RFM Resets the fractional mode Clears FM bit of STAT ...

Page 246: ... 1 N R 9d Execution STAT OM 0 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets overflow mode in status register bit 2 the OM bit Disable ALU saturation output normal mode See Also SOVM Example 4 14 59 1 ROVM Resets the overflow mode to zero ...

Page 247: ...execution completes Syntax Description RPT adrs 8 Load data memory byte to repeat counter repeat next instruction RPT imm8 Load immediate byte to repeat counter repeat next instruction See Also BEGLOOP ENDLOOP Example 4 14 60 1 RPT 0x0100 2 MOV R1 A0 A Loads the repeat counter with value stored in word data memory location 0x0100 Only 8 bits of data from this location are used The next instruction...

Page 248: ... addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location For odd RAM byte addresses the least significant bit is ignored See Also STAG RFLAG SFLAG Example 4 14 61 1 RTAG 0x0200 2 Reset the tag bit of data memory word location to 0 Note that this operation can also be done with RFLAG by loading the R6 register with 0200 2 Example 4 14 61 2 RTAG R6 0x...

Page 249: ...T clk Class RXM 1 1 N R 9d Execution STAT XM 0 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 Description Reset extended sign mode status register bit 0 the XM bit to 0 See Also SXM Example 4 14 62 1 RXM Resets the sign extension mode to normal mode Sets XM bit of STAT to 0 ...

Page 250: ... flagadrs 1 0 0 1 1 1 0 1 0 1 flagadrs Description Set flag at addressed memory location flagadrs includes two groups of memory flag adrresses global flags which are the first 64 words in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only accesses the 17th bit See Also RFLAG STAG RTAG Example 4 14 63 1 SFLAG R6 0x12 Sets the flag bit of the RA...

Page 251: ...ass SFM 1 1 N R 9d Execution STAT FM 1 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Description Sets bit 3 the FM bit in status register STAT to 1 Enable multiplier shift mode for signed fractional arithmetic Example 4 14 64 1 SFM Set fractional mode Set FM bit of STAT to 1 ...

Page 252: ...by the SV register into a 32 bit result This result is zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register Accumulator content is not changed The lower 16 bit value PL is discarded The SHL instruction can be used with a RPT instruction but without much advantage since the instructio...

Page 253: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHLAC An An next A 1 1 1 0 0 next A An 0 0 1 1 0 0 A A Description Premodify accumulator pointer if specified Shift source accumulator src or its offset left by one bit and store the result in the destination accumulator or its offset LSB of result is set to zero Example 4 14 66 1 SHLAC A1 A1 Shift accumulator A1 by one bit to the left Example 4 14 66 2 SHLAC A1 A...

Page 254: ...3 2 1 0 SHLACS An An 1 1 1 0 0 1 1 An 0 0 1 1 0 0 A A Description Shift the source accumulator string src or its offset left one bit and store the result in destination accumulator string or its offset Each accumulator is shifted individually The shifted bit is propagated through consecutive accumulators in the string Example 4 14 67 1 SHLACS A1 A1 Shift accumulator string A1 one bit to the left s...

Page 255: ... 16 bits are latched into the product high PH register The lower 16 bits of the result product low PL register is added to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulator Syntax Description SHLAPL An adrs Shift data memory word left add PL to An SHLAPL An An next A Shift An left add PL to An See Also SHLAPLS SHLTPL SHLTPLS SHLSPL SHLSP...

Page 256: ... product low PL register are added to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulators in the string Syntax Description SHLAPLS An adrs Shift data memory string left add PL to An SHLAPLS An An Shift An string left addb PL to An See Also SHLAPL SHLTPL SHLTPLS SHLSPL SHLSPLS Example 4 14 69 1 SHLAPLS A0 R4 R5 Shift the string pointed by ...

Page 257: ...ccumulator string value left nSV bits as specified by the SV register into a nS 2 x 16 bit result The result is zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register Accumulator content is not changed The lower 16 bit value is discarded SHLS instruction can be used with RPT instructio...

Page 258: ...ed into the product high PH register The lower 16 bits of the result product low PL register is subtracted from the destination accumulator or its offset This instruction propagates the shifted bit to the next accumulator Syntax Description SHLSPL An adrs Shift data memory word left substract PL from An SHLSPL An An next A Shift An left substract PL to An See Also SHLSPLS SHLTPL SHLTPLS SHLAPL SHL...

Page 259: ...or its offset This instruction propagates the shifted bit to the next accumulator Syntax Description SHLSPLS An adrs Shift RAM string left subtract PL from An SHLSPLS An An Shift An string left subtract PL from An See Also SHLSPL SHLTPL SHLTPLS SHLAPL SHLAPLS Example 4 14 72 1 SHLSPLS A0 R4 R5 Shift the string pointed by the byte address stored in R4 by nSV bits to the left subtract the shifted va...

Page 260: ... 16 bits are latched into the PH register The lower 16 bits of the result PL are transferred to the destination accumulator or its offset This instruction propagates the shifted bit into PH Syntax Description SHLTPL An adrs Shift data memory word left transfer PL to An SHLTPL An An next A Premodify APn if next A specified Shift An left transfer PL to An See Also SHLTPLS SHLAPL SHLAPLS SHLSPL SHLSP...

Page 261: ...tus register The upper 16 bits are latched into the PH register The result is transferred to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulator including one accumulator past the string length which receives the same data as PH Syntax Description SHLTPLS An adrs Shift data memory string left transfer result to An SHLTPLS An An Shift An st...

Page 262: ...C An An next a 1 1 1 0 0 next A An 0 1 0 1 1 0 A A Description Premodify accumulator pointer if specified Shift source accumulator src or its offset to right one bit and store the result into dest accumulator or its offset MSB of result will be set according to extended sign mode XM bit in the status register Example 4 14 75 1 SHRAC A1 A1 Shift right one bit the accumulator A1 Example 4 14 75 2 SH...

Page 263: ...ccumulator string right one bit and store the result into An string MSB of each accumulator in the result will be set according to extended sign mode XM bit in the status register This instruction shifts each accumulator individually 1 bit to the right so shifts from one accumulator are not propagated to the next consecutive accumulator in the string See Also SHRAC SHL SHLS SHLAPL SHLAPLS SHLSPL S...

Page 264: ...tion STAT OM 1 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Sets overflow mode in status register STAT bit 2 to 1 Enable ALU saturation output DSP mode See Also ROVM Example 4 14 77 1 SOVM Set OM bit of STAT to 1 This is the mode DSP algorithms should use ...

Page 265: ...ive see section 4 13 Description Sets the tag bit at the addressed memory location All addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location The argument adrs is interpreted as bytes For odd RAM byte addresses the least significant bit is ignored See Also RTAG RFLAG SFLAG Example 4 14 78 1 STAG R2 R5 Set TAG bit of the word in RAM byte address R2 ...

Page 266: ... 3 2 1 0 SUB An An adrs next A 0 0 0 0 A next A An adrs x dma16 for direct or offset16 long relative see section 4 13 SUB An An imm16 next A 1 1 1 0 0 next A An 0 1 0 0 0 1 A A SUB An An PH next A 1 1 1 0 0 next A An 0 1 1 0 0 0 A A SUB An An An next A 1 1 1 0 0 next A An 0 0 1 0 0 0 0 A SUB An An An next A 1 1 1 0 0 next A An 0 0 1 0 0 0 1 A SUB Rx imm16 1 1 1 1 1 1 1 0 0 0 0 1 Rx 0 0 SUB Rx R5 1...

Page 267: ... Subtract R5 from Rx See Also SUBB SUBS ADD ADDB ADDS Example 4 14 79 1 SUB A1 A1 74 Subtract 74 decimal immediate from accumulator A1 put result in accumulator A1 Example 4 14 79 2 SUB A0 A0 2 A Pre increment pointer AP0 subtract 2 from new accumulator A0 put result in accumulator A0 Example 4 14 79 3 SUB A1 A1 A1 Subtract accumulator A1 from accumulator A1 put result in accumulator A1 Example 4 ...

Page 268: ...UBB An imm8 1 0 1 0 0 1 0 An imm8 SUBB Rx imm8 1 0 1 1 0 1 k4 k3 k2 k7 k6 k5 Rx k1 k0 Description Subtract value of src byte from value of dest byte and store result in dest Note that subtraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a larger value Syntax Description SUBB An imm8 Subtract immediate byte from An SUBB Rx...

Page 269: ...in one of the listed class 1b instruc tion Offsets are allowed See Section 4 8 for detail Execution premodify AP if mod specified dest dest src for two operands dest src src1 for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly src1 is adrs TAG bit is set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SUBS An An adrs 0 0 0 1 A 1 1 An adrs x...

Page 270: ...H is maintained i e PH is subtracted from the second word of the string Also only the second word is copied to the destination string Example 4 14 81 1 SUBS A0 A0 R2 Subtract data memory string beginning at address in R2 from accumulator string A0 put result in accumulator string A0 then increment R2 by 2 Example 4 14 81 2 SUBS A1 A1 0x1220 Subtract program memory string at address 0x1220 from acc...

Page 271: ... Class SXM 1 1 N R 9d Execution STAT XM 1 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SXM 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 Description Sets extended sign mode status register STAT bit 0 to 1 See Also RXM Example 4 14 82 1 SXM Set XM bit of STAT to 1 Now all arithematic operation will be in sign extention mode ...

Page 272: ...red call Macro call Push next address onto stack load PC with the content of the address obtained by adding vector8 to 0x7F00 The execution of the instruction continues from the new PC location RET instruction is used to return from VCALL RET cannot immediately follow VCALL IRET can be used instead of RET and IRET can immidiately follow VCALL VCALL is used to call frequently used routines and take...

Page 273: ...g relative see section 4 13 XOR An An imm16 next A 1 1 1 0 0 next A An 1 1 0 0 0 1 A A XOR An An An next A 1 1 1 0 0 next A An 0 1 0 0 0 0 A A XOR TFn flagadrs 1 0 0 1 1 fig Not 1 1 0 flagadrs XOR TFn cc Rx 1 0 0 1 0 fig Not cc Rx 1 1 Description Bitwise logical XOR of src and dest Result is stored in dest If three operands are specified then logical XOR src and src1 store the result in dest Pre m...

Page 274: ... mode after the operation Example 4 14 84 5 XOR A2 A2 R2 R5 A Pre decrement pointer AP2 XOR word at effective address R2 R5 to new accumulator A2 put result in accumulator A2 Value of R2 is not modified Example 4 14 84 6 XOR TF1 0x21 XOR TF1 with the flag at global address 0x21 and store result in TF1 in STAT Example 4 14 84 7 XOR TF2 R6 0x21 XOR TF2 with the flag at effective address R6 0x21 and ...

Page 275: ... Affected dest is An OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XORB An imm8 0 0 1 0 1 1 0 An imm8 Description Bitwise logical XOR lower 8 bits of An and dest byte Result is stored in accumulator An Upper 8 bits of accumulator An is not affected See Also XOR XORS AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 86 1 XORB A2 0x45 XOR 0x45 to accumulato...

Page 276: ... are specified then logical XOR src string and src1 string store result in dest string Syntax Description XORS An adrs XOR data memory string to An string XORS An An pma16 XOR program memory string to An string store result in An string XORS An An An XOR An string to An string store result in An string See Also XOR XORB AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 86 1 XORS A0 A0 R2 XOR data memo...

Page 277: ...d dest 0 PC PC 1 Flags Affected ZF 1 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZAC An next A 1 1 1 0 0 next A An 0 0 0 1 1 0 0 A Description Zero the specified accumulator Preincrement or predecrement accumulator pointer APn if specified See Also ZACS Example 4 14 87 1 ZAC A2 Reset the content of accumulator A0 to zero Example 4 14 87 2 ZAC A1 A Preincrement AP1 by 1 Reset the content ...

Page 278: ...tions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZACS An 1 1 1 0 0 1 1 An 0 0 0 1 1 0 0 A Description Zero the specified accumulator string See Also ZAC Example 4 14 88 1 ZACS A1 Reset the content of offset accumulator string A1 to zero Example 4 14 88 2 MOV STR 32 2 ZACS A0 Reset the content of all accumulators to zero It does not matter which accumulator AP0 is pointing at since all the accumulato...

Page 279: ...r offset16 long relative see section 4 13 ADDS An An pma16 1 1 1 0 0 1 1 An 0 0 0 0 0 1 A A x pma16 ADDS An An An 1 1 1 0 0 1 1 An 0 0 1 0 1 0 A A ADDS An An PH 1 1 1 0 0 1 1 An 0 1 1 0 1 0 A A AND An adrs 0 1 0 0 0 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 AND An An imm16 next A 1 1 1 0 0 next A An 1 0 1 0 0 1 A A x imm16 AND An An An next A 1 1 1 0 0 next A An 0 1...

Page 280: ...1 An 0 1 1 0 0 1 A 0 x pma16 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 0 0 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 1 0 COR An Rx 1 1 1 0 1 0 0 An 1 1 0 Rx 1 1 CORK An Rx 1 1 1 0 1 0 0 An 1 0 0 Rx 1 1 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 n EXTSGN An next A 1 1 1 0 0 next A An 0 1 1 1 1 0 0 A EXTSGNS An 1 1 1 0 0 1 1 An 0 1 1 1 1 0 0 A FIR An Rx 1 1 1 0 1 0 0 An 0 1 0 Rx 1 1 FIRK An Rx 1 1 1 0 1 ...

Page 281: ...ng relative see section 4 13 MOV An imm16 next A 1 1 1 0 0 next A An 0 0 1 0 0 1 0 A MOV MR imm16 next A 1 1 1 0 0 next A An 1 1 1 0 0 1 0 0 MOV An An next A 1 1 1 0 0 next A An 0 0 1 1 1 0 A A MOV An PH next A 1 1 1 0 0 next A An 0 1 1 1 0 0 A A MOV SV An next A 1 1 1 0 0 next A An 1 0 1 0 0 0 A 0 MOV PH An next A 1 1 1 0 0 next A An 1 0 1 0 1 0 A 0 MOV An An next A 1 1 1 0 0 next A An 0 0 0 1 0 ...

Page 282: ...r offset16 long relative see section 4 13 MOV adrs STR 1 1 0 1 0 0 0 1 1 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs DP 1 1 0 1 0 1 0 1 0 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs SV 1 1 0 1 0 0 0 0 0 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs APn 1 1 0 1 0 0 1 An adrs x dma16 for direct or offset16 ...

Page 283: ...16 1 1 1 0 0 1 1 An 0 0 1 0 0 1 A A MOVS PH An 1 1 1 0 0 1 1 An 1 0 1 0 1 0 A 0 MOVS SV An 1 1 1 0 0 1 1 An 1 0 1 0 0 0 A 0 MOVS An PH 1 1 1 0 0 1 1 An 0 1 1 1 0 0 A A MOVS An An 1 1 1 0 0 1 1 An 0 0 1 1 1 0 A A MOVS MR An 1 1 1 0 0 1 1 An 1 0 1 1 0 0 A 0 MOVS An An 1 1 1 0 0 1 1 An 0 0 0 1 0 0 A A MOVT adrs TFn 1 1 0 1 0 1 1 1 flg adrs x dma16 for direct or offset16 long relative see section 4 13...

Page 284: ...g relative see section 4 13 MULSPLS An An 1 1 1 0 0 1 1 An 1 1 0 0 0 0 A A MULTPL An adrs 0 1 1 0 0 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MULTPL An An next A 1 1 1 0 0 next A An 1 1 0 1 1 0 A A MUL TPLS An adrs 0 1 1 0 0 0 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 MULTPLS An An 1 1 1 0 0 1 1 An 1 1 0 1 1 0 A A NEGAC An An next A 1 1...

Page 285: ... 0 0 0 0 0 0 SHL An next A 1 1 1 0 0 next A An 1 1 1 1 1 0 A 0 SHLS An 1 1 1 0 0 1 1 An 1 1 1 1 1 0 A 0 SHLAPL An adrs 0 1 1 1 1 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 SHLAPL An An next A 1 1 1 0 0 next A An 1 1 1 0 1 0 A A SHLAPLS An adrs 0 1 1 1 1 0 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 SHLAPLS An An 1 1 1 0 0 1 1 An 1 1 1 0 1 ...

Page 286: ...0 1 Rx 0 0 SUB Rx R5 1 1 1 1 1 1 1 0 0 1 0 1 Rx 0 0 SUBB An imm8 1 0 1 0 0 1 0 An imm8 SUBB Rx imm8 1 0 1 1 0 1 k4 k3 k2 k7 k6 k5 Rx k1 k0 SUBS An An adrs 0 0 0 1 A 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 SUBS An An pma16 1 1 1 0 0 1 1 An 0 1 0 0 0 1 A A SUBS An An An 1 1 1 0 0 1 1 An 0 0 1 0 0 0 0 A SUBS An An An 1 1 1 0 0 1 1 An 0 0 1 0 0 0 1 A SUBS An An PH 1 1...

Page 287: ...1 RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCF 1 0 1 0 1 0 RE RNE Conditional on RZF 1 Not condition RZF 0 0 1 0 1 1 RZP RNZP Conditional on value of Rx 0 Not available on Calls Not condition Rx 0 0 1 1 0 0 RLZP RNLZP Conditional on MSB of Rx 1 Not available on Calls Not condition MSB of Rx 0 0 1 1 0 1 L NL Conditional on ZF 0 and SF 1 Not condition ZF 0 or SF 1 0 1 1 1 0 reser...

Page 288: ... nR 3 3 ADD Rx imm16 2 2 N R 4c ADD Rx R5 1 1 nR 3 4d ADD APn imm5 1 1 N R 9c ADDB An imm8 1 1 N R 2a ADDB Rx imm8 1 1 N R 4b ADDS An An adrs Table 4 46 Table 4 46 Table 4 46 1a ADDS An An pma16 nS 4 2 N R 2b ADDS An An An nS 3 1 nR 3 3 ADDS An An PH nS 3 1 nR 3 3 AND An adrs Table 4 46 Table 4 46 1b AND An An imm16 next A 2 2 N R 2b AND An An An next A 1 1 nR 3 3 AND TFn flagadrs 1 1 nR 3 8a AND ...

Page 289: ...pma16 nS 4 2 N R 2b CMPS CMPS An An An An nS 3 1 nR 3 3 COR An Rx 3 1 3 nR 2 9a CORK An Rx 3 1 3 nR 2 9a ENDLOOP n 1 1 N R 9d EXTSGN An next A 1 1 nR 3 3 EXTSGNS An nS 3 1 nR 3 3 FIR An Rx 2 1 2 nR 2 9a FIRK An Rx 2 1 2 nR 2 9a IDLE 1 1 N R 9d IN adrs port4 Table 4 46 Table 4 46 6a IN An port6 1 1 N R 6b INS An port6 nS 4 2 nR 4 6b INTD 1 1 N R 9d INTE 1 1 N R 9d IRET 2 1 N R 5 JMP pma16 2 2 N R 7...

Page 290: ...V MR An next A 1 1 nR 3 3 MOV adrs Rx Table 4 46 Table 4 46 4a MOV Rx adrs Table 4 46 Table 4 46 4a MOV Rx imm16 2 2 N R 4c MOV Rx R5 1 1 nR 3 4d MOV SV imm4 1 1 N R 5 MOV SV adrs 1 1 nR 3 5 MOV PH adrs Table 4 46 Table 4 46 5 MOV MR adrs Table 4 46 Table 4 46 5 MOV APn adrs Table 4 46 Table 4 46 5 MOV STAT adrs Table 4 46 Table 4 46 5 MOV TOS adrs Table 4 46 Table 4 46 5 MOV adrs PH Table 4 46 Ta...

Page 291: ... 4 46 Table 4 46 1b MOVB adrs An Table 4 46 Table 4 46 1b MOVB An imm8 1 1 N R 2a MOVB MR imm8 1 1 N R 2a MOVB Rx imm8 1 1 N R 4b MOVBS An adrs Table 4 46 Table 4 46 1b MOVBS adrs 8 An Table 4 46 Table 4 46 1b MOVS An adrs Table 4 46 Table 4 46 1a MOVS adrs An Table 4 46 Table 4 46 1a MOVS adrs An Table 4 46 Table 4 46 1b MOVS An pma16 nS 4 2 N R 2b MOVS PH An nS 3 1 nR 3 3 MOVS SV An nS 3 1 nR 3 ...

Page 292: ...able 4 46 Table 4 46 1b MULAPL An An next A 1 1 nR 3 3 MULAPLS An adrs Table 4 46 Table 4 46 1b MULAPLS An An nS 3 1 nR 3 3 MULSPL An adrs Table 4 46 Table 4 46 1b MULSPL An An next A 1 1 nR 3 3 MULSPLS An adrs Table 4 46 Table 4 46 1b MULSPLS An An nS 3 1 nR 3 3 MULTPL An adrs Table 4 46 Table 4 46 1b MULTPL An An next A 1 1 nR 3 3 MULTPLS An adrs Table 4 46 Table 4 46 1b MULTPLS An An nS 3 1 nR ...

Page 293: ... RPT imm8 1 1 N R 9b RET 1 1 N R 5 RFLAG flagadrs 1 1 nR 3 8a RFM 1 1 nR 3 9d ROVM 1 1 N R 9d RTAG adrs Table 4 46 Table 4 46 5 RXM 1 1 N R 9d SFLAG flagadrs 1 1 nR 3 8a SFM 1 1 N R 9d SHL An next A 1 1 nR 3 3 SHLS An nS 3 1 nR 3 3 SHLAPL An adrs Table 4 46 Table 4 46 1b SHLAPL An An next A 1 1 nR 3 3 SHLAPLS An adrs Table 4 46 Table 4 46 1b SHLAPLS An An nS 3 1 nR 3 3 SHLSPL An adrs Table 4 46 Ta...

Page 294: ...An imm16 next A 2 2 N R 2b SUB An An PH next A 1 1 nR 3 3 SUB An An An next A 1 1 nR 3 3 SUB An An An next A 1 1 nR 3 3 SUB Rx imm16 2 2 N R 4c SUB Rx R5 1 1 nR 3 4d SUBB An imm8 1 1 N R 2a SUBB Rx imm8 1 1 N R 4b SUBS An An adrs Table 4 46 Table 4 46 1a SUBS An An pma16 2 2 N R 2b SUBS An An An 1 1 nR 3 3 SUBS An An An 1 1 nR 3 3 SUBS An An PH 1 1 nR 3 3 SXM 1 1 N R 9d VCALL vector8 2 1 N R 7a XO...

Page 295: ...0 Not condition ZF 1 or OF 0 O NO Conditional if OF 1 Not condition OF 0 RC RNC Conditional on RCF 1 Not condition RCF 0 RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCF 1 RE RNE Conditional on RZF 1 Not condition RZF 0 RZP RNZP Conditional on value of Rx 0 Not condition Rx 0 Not available on Calls RLZP RNLZP Conditional on MSB of Rx 1 Not condition MSB of Rx 0 Not available on Cal...

Page 296: ...x high input states bidirectional PD 4 inverting and PD 5 positive comparator inputs if CE 1 in IO 0x38 PD 4 triggers INT6 PD 5 triggers INT7 PD 2 triggers INT3 PD 3 triggers INT4 0x1C 8 Port D Control l if i l R W C C C C C C C C 0x00 multifunction control C 0 for interrupts IO 0x18 bit C 0 PD x as input bit C 1 PD x as output 0x20 8 Port E Data bidi i l R W E7 E6 E5 E4 E3 E2 E1 E0 external i bid...

Page 297: ...DM clock E1 Timer1 enable D4 D5 g g PD4 rising edge interrupt PD5 falling edge interrupt 0 1 MC MC E2 Timer2 enable D5 PD5 falling edge interrupt 1 MC 0 disable 1 enable 0x39 8 Interrupt Flag R W D5 D4 PF D3 D2 T2 T1 DA left unchanged Flag Register D5 PD5 falling edge interrupt flag DA DAC Timer interrupt flag unchanged Register D5 D4 PD5 falling edge interru t flag PD4 rising edge interrupt flag ...

Page 298: ...Rate 32 768 kHz oscillator reference ClkSpdCtrl Output Number of Number of IntGenCtrl p PLLM Master Clock PDM CPU Clock p Sampling Instructs Instructs DAC PDMCD Over Sampling Register Rate Rate Rate p g Rate btwn DAC btwn 8 kHz Precision Bit Factor Value Hz Hz Hz Hz Interrupts Interrupts 8 bits 1 1x 0x 0F 2 10 M 2 10 M 1 05 M 8 19 k 128 128 2x 0x 1E 4 06 M 4 06 M 2 03 M 15 87 k 128 256 4x 0x 3E 8 ...

Page 299: ... 31 M 10 24 k 128 128 2x 0x 26 5 11 M 5 11 M 2 56 M 19 97 k 128 256 4x 0x 4D 10 22 M 10 22 M 5 11 M 39 94 k 128 512 8x 0x 9B 20 45 M 20 45 M 10 22 M 79 87 k 128 1024 0 1x 0x 26 5 11 M 2 56 M 2 56 M 9 98 k 256 256 2x 0x 4D 10 22 M 5 11 M 5 11 M 19 97 k 256 512 4x 0x 9B 20 45 M 10 22 M 10 22 M 39 94 k 256 1024 9 bits 1 1x 0x 26 5 11 M 5 11 M 2 56 M 9 98 k 256 256 2x 0x 4D 10 22 M 10 22 M 5 11 M 19 9...

Page 300: ...Instruction Set Summay 4 208 Assembly Language Instructions ...

Page 301: ... MSP50P614 A reduced function C compiler called C is also available Topic Page 5 1 Introduction 5 2 5 2 MSP Software Development Tool 5 3 5 3 Requirements 5 4 5 4 Hardware Installation 5 5 5 5 Software Installation 5 6 5 6 Software Emulator 5 13 5 7 Assembler 5 33 5 8 Linker 5 38 5 9 C Compiler 5 39 5 10 Implementation Details 5 48 5 11 Beware of Stack Corruption 5 67 5 12 Reported Bugs With Code ...

Page 302: ... the speed of the PC parallel port Any MSP50C6xx device can be used in this debugging mode The MSP50P614 EPROM must be programmed to debug the code in real time The MSP50C6xx software development tool is used to program the EPROM set a breakpoint and evaluate the internal registers after the breakpoint is reached If a change is made to the code the code will need to be updated and programmed into ...

Page 303: ...hout being loaded by any low impedance reset circuit This can be accomplished by inserting a 1 kΩ resistor between the reset circuit and the reset pin and connecting the scanport reset signal directly to the reset pin See the recommended reset circuit shown in Figure 1 3 If this is not possible it would be helpful to provide an easy way to connect the MSP50C6xx scanport pins to an external level t...

Page 304: ...SI MSP50C6xx software development tool Included with MSPSI Several PGA packaged MSP50P614s EPROM eraser UV light source Application board see the following note Note The user may provide their own application board but TI has a basic applica tion board that may provide everything needed to start software develop ment This board is called the speech EVM and was designed to support sev eral TI speec...

Page 305: ...el port The red power LED should be ON The yellow Emul Prog LED comes ON when entering into emulation mode or during programming The green target LED is ON if the MSPSI is connected to a target board that has power applied Figure 5 2 Hardware Installation MSP Scanport Interface MSPSI RED LED GREEN LED YELLOW LED MSP50P614 Target development board IEEE1284 Parallel Port Cable PC Parallel port 18 V ...

Page 306: ...0 1I 0 800I 0 1I IDC2X5M HOLE DIA 0 038I PAD DIA 0 060I 0 35I 5 5 Software Installation Install the MSP50P614 MSP50C614 development tool from the supplied floppy disk by running the setup exe Installation should not take much more than one minute Following are the Software Installation steps Step 1 Run the setup exe application from Windows explorer or using the Run menu option by pressing the sta...

Page 307: ...evelopment Tools Figure 5 5 Setup Window Step 2 After setup runs the InstallShield see Figure 5 4 the setup window pops up see Figure 5 5 Step 3 Press the Next button to continue with installation or press Cancel to exit installation ...

Page 308: ...allation 5 8 Figure 5 6 Exit Setup Dialog Step 4 If you press Cancel you can return to setup by pressing Resume but ton You can exit setup by pressing Exit Setup button Figure 5 6 Figure 5 7 User Information Dialog ...

Page 309: ...ense screen and press next to the Information dialog Step 6 Type any alphanumeric value as Serial number Press Next when done Press Back to go to the previous dialog Press Cancel to exit Figure 5 8 Choose Destination Location Dialog Step 7 Select an installation directory by pressing the Browse button if the default directory is not desired Setup automatically created the installation directories ...

Page 310: ...Software Installation 5 10 Figure 5 9 Select Program Folder Dialog Step 9 Enter a new folder name in Select Program Folder dialog Step 10 Press Next to continue with installation ...

Page 311: ...Software Installation 5 11 Code Development Tools Figure 5 10 Copying Files Step 11 The program starts installation When the installation is complete an icon is also created on the desktop ...

Page 312: ...Software Installation 5 12 Figure 5 11 Setup Complete Dialog Step 12 The Setup Complete dialog message is displayed when setup is completed Press the Finish button to complete the installation ...

Page 313: ...there is a communication problem between the PC and the board Possible reasons are no power supply no chip in socket bad chip bad connection or board not working 5 6 1 The Open Screen The open screen is the initial screen blank screen of the emulator software as shown in Figure 5 12 If this is the first time you are using emulator software or you want to create a new project you should choose the ...

Page 314: ...Software Emulator 5 14 Figure 5 13 Project Menu Figure 5 14 Project Open Dialog ...

Page 315: ...nu File Insert Figure 5 15 or activate the project window by placing the mouse over it and hit the INS key Any window can be activated by placing the mouse cursor over it Assembly files extension asm and C files extension cmm can be put in a project as well as object files created by the emulator extension obj In particular do not forget to include the cmm6xx asm or cmm6xx obj once it has been ass...

Page 316: ...fy the source code and save the changes before restarting the building action 5 6 3 Description of Windows Once a new project is created or an old project is opened the following seven windows pops open Figure 5 16 Figure 5 16 MSP50P614 MSP50C614 Code Development Windows ...

Page 317: ... be changed by clicking the right mouse button on the data memory value to be changed The value is displayed in red if it has changed since the last time it was displayed To edit a memory value double click on the value to bring a small blinking cursor Keep the mouse pointer within this window and enter a new hex value Changes are only taken into account when the chip is not in run mode To add or ...

Page 318: ...similar to editing a data memory value in RAM Window The first two columns have registers labeled 00h to 1Fh the 16 bit accumulators R0 to R7 indicates indirect register values Values in parenthesis indicates the values pointed by the register using indirect addressing This value is displayed only when valid data memory address in present in the register The fourth column is all status register ST...

Page 319: ...ssage and launches the PFE EXE editor to correct the error The programmer should fix the errors save the new file and try to rebuild again The text in program window is displayed in a different color Instructions are displayed as black text Comments are always displayed as green text Preprocessor text is displayed as comments The current instruction pointed by program counter is displayed as text ...

Page 320: ...e removed while holding the SHIFT key down The 8 most recent hardware breakpoint addresses are kept in memory The user can review them by clicking on the hardware breakpoint icon which pops up the Hardware Breakpoint dialog box as shown in Figure 5 20 Hardware Breakpoint dialog allows a name to be associated with a hardware breakpoint corresponding to the breakpoint address Only one hardware break...

Page 321: ...ground either are not defined or are not active at this time The user can also use the Inspect option in the Debug menu to insert a variable in the Inspect window Figure 5 21 Inspect Dialog Figure 5 22 Inspect Window I O Ports Window The 64 I O Port values are displayed in this window Figure 5 22 They can be modified the same way most values can be ...

Page 322: ...double click the left mouse button on the filename only top level files can be removed The file becomes highlighted in yellow Hit the DEL key to remove it from the project The indentations in the display reflect the depth of inclusion of dependent files 5 6 4 Debugging a Program The software emulator allows various types of debugging The Debug menu Figure 5 23 options are explained in detail as fo...

Page 323: ...not need to have the focus to execute a Step instruction If the Step Over instruction leads into a gray area i e a program line or group of program lines that cannot be stepped into the system automatically execute the instructions until it gets out of the gray area Stepping over a line that does not contain a call or macro call is equivalent to a single step instruction Figure 5 24 Debug Menu ...

Page 324: ...ng the STOP option CTRL F10 in the debug menu Stop This menu option key equivalent CTRL F10 allows the user to stop execution of a program that was running fast or animated Do not use this option to halt a program that is running internally use the stop internal option instead Inspect This menu option is explained in section 5 6 3 under Inspect Window Show Hide Op Codes This menu option can be tog...

Page 325: ...Software Emulator 5 25 Code Development Tools Figure 5 25 EPROM Programming Dialog ...

Page 326: ...result of trace to a file with the name as project with extension trc This radio button is checked when trace mode is running Stop tracing Exit Trace Mode Run Internal This menu option launches execution on the program actually programmed on the chip In the case of MSP50P614 MSP50C614 program execution will stop if a hardware breakpoint is encountered Otherwise the user will have to stop execution...

Page 327: ...ened project object code with that in the program memory of the chip The number of location not matched is displayed 5 6 5 Initializing Chip When the Chip is RESET the hardware initializes the chip s I O registers to a know state But the data memory accumulators accumulator pointers indirect registers and other system registers are at a random state Register initializations are done by the Init me...

Page 328: ...nts for CPU window RAM Window Program Window and Project Window The Verbose C menu selection can be toggled to inhibit the insertion of extraneous comment lines in the assembly code generated by the C compiler The Debugging option is checked the monitor routine output is sent to a dump file The Misc menu option allows the user to set a certain number of options for the emulator When this option is...

Page 329: ... separated by semicolons that the C compiler will search for include files enclosed in angle brackets before searching current directory Heap start address for C compiler Beginning of Stack for C compiler Parallel port address where the Scanport interface is connected Note that the emulator tries to autodetect the scanport ...

Page 330: ...he help window Figure 5 30 is context sensitive and graphical in nature Any topic selected by pointing the mouse to the topic and clicking the left mouse button If a help is available on the topic the cursor becomes a hand cursor Some help topics launches more context sensitive help windows Learning to use the emulator is extremely fast using this graphical help system with minimal text to read ...

Page 331: ...Software Emulator 5 31 Code Development Tools Figure 5 31 Context Sensitive Help System ...

Page 332: ... prototype in the file that calls the external function To use external variables in C declare them as extern Note that only the file containing the main routine can contain global variable declarations If cmm6xx asm is included in a project file the resulting linked file will have a start vector address address 0x7FFF of _main1 corresponding to a line in cmm6xx asm that forces a jump to _main0 Th...

Page 333: ... type of error error warning short error_msg error message number short file_number file number in object file table long line_number line number in file where error occurred char info MAXIDENTIFIER 1 character string containing some information on the error struct error_struct error_list MAX_ERRORS i ASM_MAIN source_file w pass1_error error_list include_list Where source file is the assembly sour...

Page 334: ...e are explained below expression can be any numeric value Addition subtraction and multiplication are allowed Examples 128 2 2 220 5 2 0x200 equates to 0xAE 0x200 where 0x200 indicates data memory location 2 2 2 5 2 3 2 0x0F 0x04 equates to 0x15 Note that bitwise AND operator and OR operator operation is allowed 10 2 5 0x120 expression points to data memory content at 0x120 and multiplies decimal ...

Page 335: ...300 256 causes no error ELSE see IF and IFDEF END_FT This directive is created by the C compiler when it outputs assembly code to a file It marks the end of the function table used to track function calls and C variables in the emulator Users should NEVER use this directive in an assembly language program ENDIF marks the end of a conditional assembly structure started by IF or IFDEF IF expression ...

Page 336: ... directive are encountered If symbol has been defined either with a DEFINE directive or an EQU directive then all input lines are skipped until a ELSE or a ENDIF directive are encountered If a ELSE directive is encountered first all lines following it are assembled until a ENDIF directive is found Example IFDEF symbol do something here ELSE do other things here ENDIF IFNDEF symbol do something her...

Page 337: ...ession Expression defines the start up vector for the current assembly program This directive generates the following assembly code AORG 0xFFFF DATA expression which defines the start up vector of the program i e the program address where execution starts following INIT of the chip label EQU expression Associates the value of expression with label EXTERNAL symbol symbol This directive is used to i...

Page 338: ...ed by expression starting at the current RAM address label is given the value of the current RAM address If the current RAM address is not EVEN the assembler increments it by 1 before allocating the desired amount Note that RAM locations are accessed by their BYTE address in MSP50P614 MSP50C614 assembly language i e word 1 is at address 2 etc RORG expression Marks the start of a RELATIVE segment c...

Page 339: ...ws dynamic linked library DLL The current name of the DLL file is cmm6xx dll It can be invoked from any Windows program provided that the user included the file called cmm6xx lib in the Windows project The syntax of the call is extern int FAR PASCAL CMM_MAIN LPSTR source_file short warn struct cmm_input struct error_struct define MAX_LEN 256 LPSTR source_file short w i struct error_struct short pa...

Page 340: ...s encountered in the current file A file with extension ext is also generated to take care of global and external declarations that will be used by the assembler These two files are included in the opt file generated by the C compiler Note that all symbols defined in C source code are changed before being written to assembly language an underscore character is put in front of the first character o...

Page 341: ...gram ROM A good use of it would be for a sine table for example The syntax is simple for example constant int array 10 1 2 3 4 5 6 7 8 9 10 dummy 4 will create a series of DATA statements in the assembly language output file Uninitialized constants like dummy above generate a warning and are initialized to zero Constants are to be handled with care Since they cannot be accessed the same way as RAM...

Page 342: ...eemed defined this can be used in conjunction with the ifdef ifndef directives It is also possible to undefine a macro with the undefine directive With Arguments The macro name must be immediately followed by a pair of parenthesis which introduces the arguments This is completely compatible with the usual C definition Example define modulo i j i j Every occurrence of the word modulo followed by an...

Page 343: ...rective is found Note that both asm and endasm must be at the beginning of a line and that all text following them on the same line is ignored 5 9 4 5 endasm Signals the end of assembly language insertion Must be paired with a asm directive 5 9 4 6 ifdef ifndef Starts conditional assembly if token following it has been defined not been defined by a define directive These directives are terminated ...

Page 344: ... result int str1 int lg cmm_func neg_string int result int str1 int lg cmm_func copy_string int output int input int lg cmm_func rshift_string int output int input int rshift int lg ifdef _CMM cmm_func strcpy char outstring char instring cmm_func strlen char instring cmm_func calloc int nitems int size cmm_func malloc int size cmm_func free int ptr endif cmm_func test_string int string1 int string...

Page 345: ...r to compare the results of regular C programs with those of C programs The library is contained in the C source file cmm_func c It should be linked with the C equivalent of the C program and run in Borland C 5 9 7 Initializations Due in part to the architecture of the MSP50P614 MSP50C614 processor initialization is only allowed for global variables As a side effect local static variables are not ...

Page 346: ...lg 2 and puts the result in string result not_string int result int str1 int lg takes the 1 s complement of string str1 of length lg 2 and puts the result in strings result neg_string int result int str1 int lg takes the 2 s complement of string str1 of length lg 2 and puts the result in strings result test_string int string1 int string2 int lg int oper performs a logical test operation on strings...

Page 347: ...ly two constant functions implemented in C are xfer_const and xfer_single cmm_func xfer_const int out int constant_in int lg It transfers lg 2 integers from program ROM starting at address constant_in to RAM starting at address out Note that constant_in is not doubled because it is used in A0 in a MOV A0 A0 operation The C compiler takes care of this cmm_func xfer_single int out int constant_in tr...

Page 348: ...egers a and b to be compared are in A0 and A0 CMP A0 A0 A0 contains a A0 contains b A0 A0 ACO AZ ANEG 5 0 1 0 0 5 1 1 0 0 0 5 0 0 1 1 5 0 0 1 0 0 1 1 0 5 5 1 1 0 FFFF 0 1 0 1 0 FFFF 0 0 0 FFFF FFFF 1 1 0 FFFF FFFE 1 0 0 FFFE FFFF 0 0 1 Signed comparison of a and b a is in A0 b is in A0 Assembly Test Condition _eq a b AEQ _ne a b AEQ _lt a b ALZ _le a b AGT _ge a b ALZ _gt a b AGT ...

Page 349: ...unctions return their results via A0 but there is no guarantee that the absolute value of the A0 pointer is not changed by the function To compare integers a and b after loading a in A0 and b in A0 do a vector call to the appropriate comparison routine Assembly Vector _eq 0 _ne 1 _lt 2 _le 3 _ge 4 _gt 5 _ult 6 _ule 7 _uge 8 _ugt 9 _lneg 10 We return the result of the comparison in Flag 2 set for T...

Page 350: ...e R7 for stack pointer and yet another register for BP REG_BP R5 because of its special arithmetic capabilities Before a function is called the arguments are pushed on the stack first argument first The function call automatically pushes the return address on the stack Immediately upon entering the function body the current BP is pushed on the stack to preserve it so that the stack pointer now poi...

Page 351: ... TOS register on RET 1 next PC TOS 2 transfer R7 to TOS 3 decrement R7 We can freely manipulate R7 before a CALL Ccc and after a RET to load and unload arguments to and from the stack Of course it would be a bad idea to mess with the TOS register in the body of a function 5 10 4 Programming Example The following example implements string multiplication i e the multiplication of 2 integer strings T...

Page 352: ...sult into string p of length lgp 2 int sign i j int mm1 mm2 pp sign 1 mm1 calloc sizeof int lgm1 2 mm2 calloc sizeof int lgm2 2 pp calloc sizeof int lgp 2 if test_string m1 0 lgm1 LTS_N neg_string mm1 m1 lgm1 sign 1 else copy_string mm1 m1 lgm1 if test_string m2 0 lgm2 LTS_N neg_string mm2 m2 lgm2 sign 1 else copy_string mm2 m2 lgm2 for j 0 j lgp 2 j p j 0 for i 0 i lgm2 2 i for j 0 j lgp 2 j pp j...

Page 353: ...ter_ram irx RAMSTART_ASM equ RAMEND_INT include asm_ram irx Here the sub files are inter_ram irx and asm_ram irx The allocation for inter_ram irx begins at memory location 2 This is because the memory location 0 is reserved for use by the C compiler The allocation for asm_ram irx begins where the allocation ended for inter_ram irx More irx files can be chained on in this manner and all of the allo...

Page 354: ...s It is also important not to alter the contents of registers R5 and R7 R7 is the stack pointer and R5 is a frame pointer used in C to C function calls Parameters are passed on the stack and the return value is always int and always located in a0 The stack usage for function calls is as follows C to C function call The stack is shown after the operation on the bottom is performed R7 Param 2 Param ...

Page 355: ... the R5 old R5 C function call R7 Return Addr Return Addr Return Addr Return Addr Return Addr Return Addr Param 2 Param 2 Param 2 Param 2 Param 2 Param 2 Param 1 Param 1 Param 1 Param 1 Param 1 Param 1 R5 Stack data R5 Stack data Stack data Function call ADDB R7 2 MOV 0 R7 MOV R7 R5 MOV R5 0 ...

Page 356: ...5 old R5 old R5 old R5 old R5 Return Addr R7 Return Addr Return Addr Return Addr Return Addr Return Addr Param 2 Param 2 R7 Param 2 Param 2 Param 2 Param 2 Param 1 Param 1 Param 1 Param 1 Param 1 Param 1 Stack data R5 Stack data R5 Stack data SUBB R7 2 MOV A0 R7 RET MOV 0 A0 MOV R5 0 ...

Page 357: ...Implementation Details 5 57 Code Development Tools old R5 old R5 Return Addr Return Addr Param 2 Param 2 Param 1 Param 1 R7 R5 Stack data SUBB R7 4 ...

Page 358: ...58 C to ASM function call The stack is shown after the operation on the bottom is performed R7 Param 2 Param 2 R7 Param 1 Param 1 Param 1 Param 1 R7 R5 Stack data R5 Stack data R5 Stack data Before call Parameter 1 Parameter 2 ...

Page 359: ... Addr Return Addr Param 2 Param 2 Param 1 Param 1 R5 Stack data Function call C to ASM function return Return Addr Return Addr Return Addr Return Addr R7 Param 2 Param 2 Param 2 Param 2 Param 1 Param 1 Param 1 Param 1 R5 Stack data R7 R5 Stack data RET SUBB R7 4 ...

Page 360: ...3_ISR PORTF_ISR GLOBAL reset DUMMY_ISR EXTERNAL _main0 include ram ram irx include control control irx include control io_ports irx include control control asm Reset Begin at init614 in INIT ASM This sets the 614 to run at 8 MHz 10 bit DAC at 8 kHz reset reset include control init asm _MAINASM The start of the assembly code which is called from main routine in main cmm _asminit nop pause for breat...

Page 361: ...t _prtb out 0x08 a0 write to PortB ret _prtc out 0x10 a0 write to PortC ret _prtd out 0x18 a0 write to PortD ret _prte out 0x20 a0 write to PortE ret _out_port_access table for table lookup DATA _prta DATA _prtb DATA _prtc DATA _prtd DATA _prte called from C int iport char Port Reads data from the I O port specified by the letter Port Example int data iport F Read port F _iport mov a0 r7 2 port ad...

Page 362: ...he letter Port Example cport B 0xFF Configure all bits of Port B as output _cport mov a0 r7 4 port address mov a0 r7 2 data add a0 _cont_port_access A find the location in the table mov a0 a0 get the value of the label in the table jmp a0 jump to the label from the table _cprta out 0x04 a0 write to PortA control ret _cprtb out 0x0C a0 write to PortB control ret _cprtc out 0x14 a0 write to PortC co...

Page 363: ...a0 a0 mov tempa a0 mov r4 tempa _rep call wait1ms wait 1ms jrnzp _rep r4 decrement counter by 2 ret Pause for 1ms Input Output Uses Calls wait200us wait1ms call wait200us call wait200us call wait200us call wait200us call wait200us ret Pause for 200us Input Output Uses wait200us rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 256 2 nop rpt 64 2 ...

Page 364: ...hen all LED s will light for 5 seconds As soon as an incorrect sequence or portion of the sequence is detected the LED s will flash and the procedure will repeat Due to the indication of an incorrect sequence partway through there are only 4 combinations needed to find a sequence of length 4 The difficulty of determining the code could be increased greatly by using multiple key combinations MS7 an...

Page 365: ... from F wait 100 delay 100ms for key debouncing l iport F read port F while l 0xFF wait for key release wait 100 delay 100ms for key debouncing l iport F read port F if x i k compare to correct input locked 1 if incorrect then lock and return return locked end for i 0 i 4 i return locked If the program reaches this return then all inputs were correct and the main program can unlock cmm_func main c...

Page 366: ... wait 100 oport B 0x00 wait 100 oport B 0xFF wait 100 oport B 0x00 wait 100 oport B 0xFF wait 100 else If the correct inputs were given oport B 0x00 Light all LED s wait 5000 Keep lit for 5 seconds unlock the door end for return ...

Page 367: ...y the hardware This problem may not be easily observed in the system level But once it happens it is very difficult to debug Use the following method to modify stack pointer instead MOV A0 R7 2 2 ADD A0 address MOV A0 A0 ADD A0 R7 2 1 MOV A0 A0 RET This method will not have the stack corruption problem since the MOV instruc tion performs the entire operation either before or after an interrupt 5 1...

Page 368: ...5 68 ...

Page 369: ...initialization sequence resistor trim setting synthesis code memory over lays and ROM usage Topic Page 6 1 Application Circuits 6 2 6 2 MSP50C614 MSP50P614 Initialization Codes 6 4 6 3 Texas Instruments C614 Synthesis Code 6 8 6 4 ROM Usage With Respect to Various Synthesis Algorithms 6 14 Chapter 6 ...

Page 370: ...ftheScanPortInterface The same applies for the 1 kΩ resistor which appears at the RESET pin the resistor may be shorted if not using the Scan Port However the footprintfor the resistor is stronglyrecommended for any C614 production board Refer to the Important Note regarding Scan Port Bond Out appearing in Chapter 7 Minimum Circuit Configuration for the C614 P614 Using Resistor Trimmed Oscillator ...

Page 371: ...ire use of the Scan Port Interface The same applies for the 1 kΩ resistor which appears at the RESET pin the resistor may be shorted if not using the Scan Port However the footprint for the resistor is strongly recommended for any C614 production board Refer to the Important Note regarding Scan Port Bond Out appearing in Chapter 7 5 V 0 1 µF 5 3300 pF OSCIN OSCOUT PLL DACP DACM VPP VDD 1N914 32 Ω ...

Page 372: ...ain which is the beginning of MSP50P614 MSP50C614 user code It is recommended that INIT_DEVICE_614 is per formed immediately after RESET to ensure that device initialization is always performed at RESET Users modifying the initialization routine is not recom mended The initialization routine does the following Disables all interrupts Zeros out all accumulators Zeros out all memory Starts oscillato...

Page 373: ...ed in TIM1 register 6 Zeros all system registers except R7 STACK Turn off TIMER 2 rather than leave it running Modified to cope with 6 bit trim value Top 5 bits go to bits 15 11 in ClkSpdCtrl LSB of trim goes to bit 9 in ClkSpdCtrl A fairly basic but compact initialization routine for the 614 This sets the 614 to run at 8 MHz 10 bit DAC at 8 kHz C614FLAG EQU 0 EQU 1 if MSP50C614 part RESISTORTRIM ...

Page 374: ...MR 0x000 clear multiplier register Choose the source for the reference oscillator Set the PLLM register accordingly in this case for a CPU clock of 8 MHz and then set TIMER 2 to a 200 ms period Go to sleep do an IDLE and wake up when the clock has reached full speed and is stable if CRO_FLAG mov a0 CROENABLE enable crystal oscillator else if C614_FLAG in a0 RTRIM for C614 read trim value from regi...

Page 375: ... idle go to sleep nop wake up 200 ms later clock running at full speed nop nop Upon reset all ports are set to input and port G output is set low 0x0000 Therefore it remains only to enable the pullups on port F in a0 IntGenCtrl or a0 PFPULLUPS enable port F pullups and a0 TIM2IMR turn off TIMER 2 interrupt and a0 TIM2ENABLE turn off TIMER 2 out IntGenCtrl a0 Set the DAC to 10 bits C3x style For C5...

Page 376: ...nport are both illuminated before attempting to start the code development tool Click on Start menu go to Programs EMUC6xx and click on MSP50C6xx development tool menu item To open a project click on Project New Project and select the desired project file e g C 614 PROJECTS MELP1 MELP1 RPJ Click on Project Build to assemble and link the constituent files of the project Then click Debug Eprom Progr...

Page 377: ...rogram is sitting in a loop and scanning SW1 and SW2 Pressing SW1 launches the MELP synthesizer into 11 character phrases Pressing SW2 begins a more complex sequence of events One MELP phrase is synthesized and then the 614 goes into midsleep mode the LEDs will cease flashing This sleep mode can be exited by pressing SW1 after which another character voice will be synthesized Finally if an EPROM i...

Page 378: ...e 6 10 spk_ram irx melp melp obj melp irx modules 605 605 asm 605 irx general init asm sleep asm io_ports irx isr dac_isr asm tim1_isr asm tim2_isr asm ram ram irx speech melp 1kbps qfm 24kbps qfm main asm main irx main_ram irx melp1 rpj ...

Page 379: ... Init asm Initialization code to set the clock speed etc Edit at your peril Sleep asm Routines to enter and wake up from the light mid and deep sleep Io_ports irx Control register and bitmask definitions Dac_isr asm DAC interrupt service routine Tim1_isr asm Timer 1 interrupt service routine keyscan Tim2_isr asm Timer 2 interrupt service routine LED flash Ram irx RAM overlay for the entire program...

Page 380: ...de just below the shriek4 label shriek4 movb a0 4 call do_shriek To test this code build the MELP2 project and program another P614 Set a breakpoint at shriek4 and then do a Run Internal yellow lightning black centipede icon Step over press F8 and the accumulator 00 will be 0004 after the movb instruction Step over once more and the accumulator 00 will be 0018 after calling the do_shriek function ...

Page 381: ...y to accommodate multiple synthesis algorithms If the user is interested in using the data memory the starting memory location has to start from the last memory location used by the program 2 The synthesis code has a file named MAIN_RAM IRX This file is provided for maintaining overlay New variables are added as follows bytes byte1 equ RAMSTART_CUSTOMER 1 byte2 equ byte1 1 words word1 equ byte2 2 ...

Page 382: ...speech duration is used for each algorithm The bit rates and program sizes given in this table are only approximations The estimates are applicable at the time of this printing but they are subject and likely to change Also the data rate is sometimes dependent on the properties of the speech C614 Total ROM Storage 32 768 words BIST MELP program MELP speech data rate 2 4 k bits per second 2048 word...

Page 383: ...ent cycle and ordering forms are included in this chapter Topic Page 7 1 Mechanical Information 7 2 7 2 Customer Information Fields in the ROM 7 7 7 3 Speech Development Cycle 7 8 7 4 Device Production Sequence 7 8 7 5 Ordering Information 7 10 7 6 New Product Release Forms 7 10 Chapter 7 ...

Page 384: ...ystem problems For this reason these pins MUST be bonded out on any C614 production board Furthermore it is recommended that these pins be connected to test points so the development tool can be connected Since the development tool requires VDD and VSS test points connected these signals are also needed The application circuits appearing in section 6 1 show the minimum recommended configuration fo...

Page 385: ... NC 4 NC 29 NC 54 NC 79 DACM 5 PG7 30 NC 55 NC 80 VCC3 DA 6 PF6 31 X2 56 NC 81 DACP 7 PF5 32 X1 57 NC 82 VCC 8 PF4 33 PLL 58 PC7 83 PF7 9 PF3 34 PA7 59 PC6 84 PF6 10 PF2 35 PA6 60 PC5 85 PF5 11 PF1 36 PA5 61 PC4 86 PF4 12 PF0 37 PA4 62 PC3 87 PF3 13 SCANOUT 38 PA3 63 PC2 88 PF2 14 TEST 39 PA2 64 PC1 89 PF1 15 SYNC 40 PA1 65 PC0 90 PF0 16 SCANCLK 41 PA0 66 GND2 91 NC 17 SCANIN 42 GND1 67 VCC2 92 PG...

Page 386: ...45 13 80 16 95 50 51 31 30 12 35 TYP 1 03 0 73 0 25 Seating Plane 0 25 MIN Gage Plane 0 38 0 22 80 1 81 100 22 95 23 45 20 20 19 80 2 50 2 90 3 40 MAX 18 85 TYP 0 7 M 0 13 0 65 0 10 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 022 ...

Page 387: ... array packaged P614 is available The P614 s PGA package is shown in Figure 7 2 Figure 7 2 120 Pin Grid Array Package for the Development Device P614 extra pin 1 2 3 4 5 6 7 8 9 N M L K J H G F E D C B A 10 9 8 7 6 5 4 3 2 1 N M L K J H G F E D C B A BOTTOM VIEW TOP VIEW 11 12 13 1112 13 10 Note The PGA package is only available in limited quantities for development purposes ...

Page 388: ...anout H VDD PD7 PD6 pgmpuls SYNC scanclk G VSS PC1 PC0 bottom view RESET scanin PE7 F PC2 PC3 PC4 PE4 PE5 PE6 E PC5 PC6 nc PE0 PE2 PE3 D PC7 nc nc extra nc VSS PE1 C nc nc nc nc PB1 PB5 VSS PA3 PA7 nc nc nc nc B nc nc nc PB0 PB3 PB6 PA0 PA2 PA5 PLL OSCOUT nc nc A nc nc nc PB2 PB4 PB7 VDD PA1 PA4 PA6 OSCIN nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 It is important to provide a separate decoupling capacito...

Page 389: ...tored in locations 0x0006 through 0x000C Assuming these addresses are not specifically read protected by the ROM security they are read accessible to the programmer The fields appear as follows MSP50C614 EPROM Test Area Customer Information Fields 16 bit wide the 17th bit is ignored Address Field Description Example Value 0x0006 Device number 0x0614 for C614 0x0007 Mask number assigned by TI 0x000...

Page 390: ...diting for certain algo rithms and to evaluate synthesis results through playback of encoded speech Design of the software and hardware development of software and prototype construction are all customer dependent aspects of the speech development cycle 7 4 Device Production Sequence For the speech development group at TI to accept a custom device program the customer must submit a new product rel...

Page 391: ...devices is incurred by the customer A minimum purchase is required during the first year of production Customer Sends Code in QBN or TITAG format and completes Section 1 of the NPRF TI completes Section 2A of NPRF and sends verifi cation code in QBN for mat with BIST included NPRF form to customer Customer verifies code is correct Customer signs Section 3 of the NPRF and sends it to TI TI generate...

Page 392: ... With Memory 614 XXX X X Family Member ROM Code Revision Letter Package or Die PJM Loopin QFP Preliminary Y Die 7 6 New Product Release Forms The new product release form is used to track and document all the steps in volved in implementing a new speech code onto one of the parent speech de vices This section is to be completed by the customer and sent to TI along with the code ...

Page 393: ...original data I hereby certify that the TI generated verification data has been checked and found to be correct and I authorize TI to generate masks prototypes and risk units in accordance with the purchase order in Section 1 above In addition By _____________________________________________ Title __________________________________________ Date________________ SECTION 4 APPROVAL OF PROTOTYPES AND ...

Page 394: ...7 12 ...

Page 395: ...ontains preliminary data for the MSP50C605 device Note MSP50C605 MSP50C605 is in the Product Preview stage of development For more in formation contact your local TI sales office Topic Page A 1 Introduction A 2 A 2 Features A 2 A 3 Architecture A 2 Appendix A ...

Page 396: ...t configurable IO Data ROM page DRP Port G 0x2C General purpose 16 bit output Data ROM address DRA A 2 Features 30k word ROM customer program memory Approximately 1 835 Mbits data ROM 8 MHz uDSP core 32 input or output pins J 24 Pins general purpose bit configurable as input or output J 8 input pins with programmable 100 Ω pull up resistors 1 bit comparator with edge detection interrupt service IM...

Page 397: ... lower 16 bits of the address to be read is provided into IO port DRA register 0x2C the upper 2 bits goes into IO port DRP regis ter 0x08 After 1 5 instruction cycle delay the 8 bit data appears at IO port DRD 0x00 Discharging time is always 3 processor cycle and data is latched to port DRD during this time There is 3 5 page in MSP50C605 pages 0 1 and 2 are full page 3 is half Using 1Kbps MELP alg...

Page 398: ...ESET DAC 0x30 32 Ohm PDM DAC M DAC P SYNC TEST Scan Interface SCAN IN SCANOUT SCANCLK EP ROM 32k x 16 1 bit User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF Test Area 0x0000 to reserved 0x07FF D port I 0 DATA 0x18 8 PD0 7 Comparator 1 bit PD5vs PD4 OSC Reference PLL Filter PLL OSC OUT Crystal Referenced 32 768 kHz Resistor Trimmed 32 kHz nominal OSC IN or or Break Point Emulation OTP Program...

Page 399: ... Call Vectors 255 x 17 bit overlaps interrupt vector locations 0x 08 DRP0 3 0x 10 PC0 7 data 0x 20 PC0 7 ctrl 0x 24 PD0 7 data 0x 28 PD0 7 ctrl 0x 2C PE0 7 data 0x 30 PE0 7 ctrl 0x 34 PF0 7 data 0x 38 DRA0 15 0x 39 DAC data 0x 3A DAC ctrl 0x 3B IntGenCtrl IFR 0x 3D PRD1 0x 3E TIM1 0x 3F 0x 14 ClkSpdCtrl 0x 18 PRD2 0x 1C TIM2 0x7F00 0x 2F RTRIM Usable Interrupt Vectors 8 x 17 bit 0x7FFE Unusable In...

Page 400: ...Architecture A 6 Figure A 3 MSP50C605 100 Pin PJM Package MSP50C605 100 PIN PJM PLASTIC PACKAGE 1 80 81 100 30 31 50 51 ...

Page 401: ...1 DACP 7 VCC1 32 NC 57 PC7 82 VCC 8 SCAN_OUT 33 NC 58 PC6 83 PF7 9 TEST 34 NC 59 PC5 84 PF6 10 SYNC 35 NC 60 PC4 85 PF5 11 SCNCLK 36 NC 61 PC3 86 PF4 12 SCANIN 37 NC 62 PC2 87 PF3 13 INITZ 38 NC 63 PC1 88 PF2 14 PE7 39 NC 64 PC0 89 PF1 15 PE6 40 NC 65 GND 90 PF0 16 PE5 41 NC 66 VCC2 91 GND 17 PE4 42 NC 67 PD7 92 NC 18 PE3 43 NC 68 PD6 93 NC 19 PE2 44 NC 69 PD5 94 NC 20 PE1 45 NC 70 PD4 95 NC 21 PE...

Page 402: ...A 8 ...

Page 403: ...reliminary data for the MSP50C604 device Note MSP50C604 MSP50C604 is in the Product Preview stage of development For more in formation contact your local TI sales office Topic Page B 1 Introduction B 2 B 2 Features B 2 B 3 Architecture B 2 B 4 Packaging B 8 Appendix B ...

Page 404: ...z crystal 640 word RAM PDM DAC w direct speaker drive 32 ohm 1 bit comparator with edge detection interrupt service IMPORTANT Not currently supported Serial scan port for in circuit emulation monitor test Host Mode J 14 general purpose I O pins J Can generate interrupts Slave Mode J Works as microprocessor peripheral J STROBE R W lines for host read write control J INPUTREADY OUTPUTREADY for hands...

Page 405: ... mode and slave mode In host mode 6 of the 14 pins are the same as pins PD0 to PD5 on port D of the MSP50C614 The other 8 pins are the same as one of I O port C All of the functions of port D on the MSP50C614 are available on the MSP50C604 in cluding four interrupts the conditional branch control and the comparator In slave mode only PD4 and PD5 are be available for general purpose I O in cluding ...

Page 406: ... 1 bit User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF Test Area 0x0000 to reserved 0x07FF D port I 0 Control 0x1C DATA 0x18 Comparator 1 bit PD5vs PD4 OSC Reference PLL Filter PLL OSCOUT Crystal Referenced 32 768 kHz Resistor Trimmed 32 kHz nominal OSCIN or or Break Point Emulation OTP Program Serial Comm TIMER2 PRD2 TIM2 0x3E 0x3F Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem Addr...

Page 407: ... data on port C pins PC0 PC7 4 Host takes STROBE low 5 On rising edge of STROBE data latched into port A INRDY goes high rising edge interrupt INT3 is activated 6 When input latch is read INRDY goes low to restart cycle B 3 6 Host Read Sequence 1 MSP50C604 signals readiness to receive data by taking OUTRDY low 2 Host takes R WZ high 3 Host takes STROBE low 4 Data port C sets as output by MSP50C604...

Page 408: ...0x 027F 0x 0000 Data Memory RAM 640 x 17 bit Macro Call Vectors 255 x 17 bit overlaps interrupt vector locations 0x 10 PC0 7 data PC0 7 ctrl PD0 7 data PD0 7 ctrl 0x 2C 0x 30 0x 34 0x 38 PG0 0x 39 DAC data 0x 3A DAC ctrl 0x 3B IntGenCtrl IFR 0x 3D PRD1 0x 3E TIM1 0x 3F 0x 14 ClkSpdCtrl 0x 18 PRD2 0x 1C TIM2 0x7F00 0x 2F RTRIM Usable Interrupt Vectors 8 x 17 bit 0x7FFE Unusable Interrupt Vectors re...

Page 409: ...derflow Timer 2 underflow 3 7FF3h Port D2 Rising edge 4th Port D2 goes high Host write 4 7FF4h Port D3 Falling edge 5th Port D3 goes low Host read 5 7FF5h Port F Falling edge 6th Reserved not used Reserved not used 6 7FF6h Port D4 Rising edge 7th Port D4 goes high Port D4 goes high 7 7FF7h Port D5 Falling edge Lowest Port D5 goes low Port D5 goes low INT6 and INT7 may be associated with the compar...

Page 410: ...in VCC 1 NC 17 PC6 33 GND 49 VCC3 2 NC 18 PC5 34 NC 50 PD3 3 NC 19 PC4 35 NC 51 PD2 4 NC 20 PC3 36 NC 52 PD1 5 NC 21 PC2 37 NC 53 PD0 6 NC 22 PC1 38 NC 54 TEST 7 NC 23 PC0 39 NC 55 SCAN_OUT 8 NC 24 PD7 40 NC 56 SYNC 9 NC 25 PD6 41 NC 57 SCAN_CLK 10 NC 26 PD5 42 NC 58 SCAN_IN 11 NC 27 PD4 43 NC 59 RESET 12 NC 28 VCC1 44 NC 60 X2 13 NC 29 DACM 45 NC 61 X1 14 NC 30 VCC2 46 NC 62 PLL 15 NC 31 DACP 47 ...

Page 411: ... B 3 MSP50C604 Slave Mode Signals INRDY OUTRDY R WZ STROBE PC0 PC7 Data latched to Port A New Data Valid Data Host write sequence Host read sequence Figure B 4 MSP50C604 64 Pin PJM Package MSP50C604 64 PIN PJM PLASTIC PACKAGE 32 48 33 49 17 16 1 64 ...

Page 412: ...Packaging B 10 ...

Page 413: ...C 1 Appendix A MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed signal pro cessor Topic Page C 1 MSP50C605 Data Sheet C 2 Appendix C ...

Page 414: ...C 2 C 1 MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed signal pro cessor ...

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