7.4 Connections for Unused Pins
All unused pins must be left as no connect (NC) pins.
Table 7-3. Connections for Unused Pins
FUNCTION
SIGNAL DESCRIPTION
PIN NUMBER
ACCEPTABLE PRACTICE
DIO
Digital input or output
3, 9, 10, 12, 18,
19, 22, 42, 53, 54
Wake up I/O source should not be floating
during hibernate. All the I/O pins will float
while in Hibernate and Reset states. Ensure
pullup and pulldown resistors are available on
board to maintain the state of the I/O. Leave
unused GPIOs as NC
No Connect
NC
20, 21, 33, 39,
41, 45
Unused pin, leave as NC.
SOP
Configuration sense-on-power
23, 24, 34
Leave as NC (Modules contain internal 100
kΩ pull down resistors on the SOP lines). An
external 10 kΩ pull up resistor is required for
factory restore. See
.
Reset
RESET input for the device
35, 36
There is an internal 100 kΩ pull-up
resistor option from the nRESET pin to
VBAT_RESET. Note: VBAT_RESET is not
connected to VBAT1 or VBAT2 within the
module. The following connection schemes
are recommended:
•
Connect nRESET to a GPIO from the
host only if nRESET will be in a defined
state under all operating conditions.
Leave VBAT_RESET unconnected to
save power.
•
If nRESET cannot be in a defined state
under all operating conditions, connect
VBAT_RESET to the main module power
supply (VBAT1 and VBAT2). Due to the
internal pull-up resistor, a leakage current
of 3.3 V / 100 kΩ is expected.
SWRS225D – FEBRUARY 2019 – REVISED MAY 2021
16
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