10.1.3 Typical Application
shows the typical application schematic using the CC3135MOD module.
VBAT_CC
GND
EXTERNAL
PROGRAMMING
1
2
3
4
5
6
J1
10k
R1
VBAT_CC
0.1uF
C2
0.1uF
C1
GND
GND
SEE TABLE 4-1 FOR
VBAT_RESET and nRESET
CONNECTION OPTIONS
SOP[2:0] USED TO CONFIGURE
Matching circuit shown below is for
the antenna. The module is matched
internally to 50 . Final solution
Ω
may require antenna matching
optimization with a pi-network.
100uF
C4
100uF
C5
GND
GND
VBAT_CC
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
RF_ABG
GND GND
3nH
L1
GND
1
2
E1
BOOT MODES (TABLE 5-5)
RS232_TX
RS232_RX
UART_TX
UART_RX
UART1_RTS
CC_UART1_TX
UART1_CTS
CC_UART1_RX
CC_SPI_DIN
CC_SPI_CLK
CC_IRQ
CC_SPI_DOUT
CC_SPI_CS
HOST CONTROL
CC_nHIB
HOST INTERFACE
(Ensure that nHIB line
does not
fl
oat at any time.)
3.3pF
C3
DIO13
10
GND
2
GND
1
GND
16
GND
27
GND
28
GND
30
GND
32
GND
38
GND
43
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
HOST_INTR
11
HOST_SPI_CLK
5
HOST_SPI_DIN
6
HOST_SPI_DOUT
7
HOST_SPI_CS
8
FLASH_SPI_MISO
13
FLASH_SPI_CS_IN
14
NC
33
FLASH_SPI_CLK
15
NC
41
DIO30
42
DIO10
3
NC
45
DIO8
53
DIO9
54
FLASH_SPI_MOSI
17
DIO24
18
NC
20
DIO29
22
GND
25
GND
26
DIO12
9
DIO23
12
GND
29
RESERVED
21
DIO28
19
RF_ABG
31
SOP0
34
SOP1
24
SOP2
23
TEST_58
48
TEST_59
49
TEST_60
50
TEST_62
52
UART1_RX
47
UART1_TX
46
UART1_CTS
51
UART1_RTS
44
VBAT_RESET
36
VBAT2
40
VBAT1
37
NC
39
HIB
4
RESET
35
CC3135MODRNMMOBR
CC1
This is the reference schematic and not an actual board design. For a full operational reference design, see the
CC3135MOD Hardware Design Files
Figure 10-3. CC3135MOD Module Reference Schematic
SWRS225D – FEBRUARY 2019 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
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