Texas Instruments SLLU040A, User Manual

Overview

2-2

2.1

Overview

LVDS driver output characteristics are specified in the TIA/EIA-644 standard.
LVDS drivers nominally provide a 350-mV differential signal, with a 1.25-V
offset from ground. These levels are attained when driving a 100-

Ω

 differential

line-termination test load (see Figure 2-1). In real applications, there may be
a ground potential between a driver and receiver(s). The driver must drive the
common-mode load presented by the receiver inputs and the differential load.
A TIA/EIA-644-A compliant LVDS driver is required to maintain its differential
output with up to 32 standard receivers. The receiver load is represented by
the 3.74-k

Ω

 resistors shown in Figure 2-1.

Figure  2-1. TIA/EIA-644-A LVDS Driver Test Load

_

+

A

B

V

OD

100 

Ω

3.74 k

Ω

3.74 k

Ω

0 V 

≤

 V

test

≤

 2.4 V

D

LVPECL drivers are generally loaded with 50-

Ω

 resistors to a termination bias

voltage, V

T

. V

T

 is usually 2-V below the supply voltage of the driver circuit.

When the driver operates from a 3.3-V supply, V

T

 is set to approximately 1.3 V.

CML drivers are generally loaded with 50-

Ω

 resistors to a termination voltage,

V

TT

. V

TT

 can either be equivalent to the supply voltage of the driver circuit

(equal to V

CC

) or set to 2.5 V or 1.8 V, irrelevant to the supply voltage. If de-

sired, the SN65CML100 can be configured to drive a dual 50-

Ω

 load. In this

configuration one 50-

Ω

 resistor (tied to the termination voltage V

TT

) is placed

near the output of the SN65CML100 and a second 50-

Ω

 resistor (also tied to

V

TT

) is placed near the end of the transmission line.

The EVM has been designed to support the SN65LVDS100 LVDS-output
device, the SN65LVDS101 LVPECL-output device, and the SN65CML100
CML-output device. By using the three power jacks (J1, J2, and J3), as well
as installing termination resistors (R2, R3, and R4), different methods of
termination and probing can be used to evaluate the device output
characteristics. The typical setup for the SN65LVDS100 is shown in
Figure 2-2.