Texas Instruments SLLU040A, User Manual

Page 1: ...2 GBPS Differential Repeater Evaluation Module November 2002 High Performance Linear Interface Products User s Guide SLLU040A ...

Page 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Page 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Page 4: ...inty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 125 C The EVM is designed to operate properly with certain components above 125 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transist...

Page 5: ...Required Chapter 3 EVM Construction Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The informatio...

Page 6: ...e Number SN65LVDS100 101 SLLS516 SN65CML100 SLLS547 FCC Warning This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interfe...

Page 7: ...aterials 3 3 3 3 Board Stackup 3 4 3 4 Board Layer Patterns 3 5 Figures 1 1 EVM With SN65LVDS100 Installed 1 2 1 2 Schematic of EVM Signal Path 1 3 2 1 TIA EIA 644 A LVDS Driver Test Load 2 2 2 2 EVM Power Connections for SN65LVDS100 Evaluation 2 3 2 3 External Termination for Differential CML or LVPECL Inputs to EVM 2 4 2 4 External Termination for Single Ended LVPECL Inputs to EVM 2 5 2 5 Typica...

Page 8: ...Contents viii ...

Page 9: ...llows evaluation of the SN65LVDS100 SN65LVDS101 and SN65CML100 differential repeaters translators This user s guide gives a brief overview of the EVM setup and operation instructions and typical test results that can be expected Topic Page 1 1 Overview 1 2 1 2 Signal Paths 1 3 Chapter 1 ...

Page 10: ...erence voltage to support receiving of single ended LVPECL input signals or biasing of ac coupled inputs The EVM can be ordered with the SN65LVDS100 SN65LVDS101 or SN65CML100 installed Orderable EVM part numbers are shown in Table 1 1 Table 1 1 Ordering Information EVM Part Number Installed Device SN65LVDS100EVM SN65LVDS100DGK SN65LVDS101EVM SN65LVDS101DGK SN65CML100EVM SN65CML100DGK Detailed info...

Page 11: ...sed to provide power to and a ground reference for the EVM The use of these power jacks is addressed later Chapter 3 also provides a parts list for the EVM as well as an indication of which components are installed when shipped Figure 1 2 Schematic of EVM Signal Path NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 010 µF DUT_MSOP8 DUT1 VCC01 VCC C11 010 µF R2 Uninstalled J6 GND J7 GND R4 Uninst...

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Page 13: ... and Equipment Required This chapter examines the setup and use of the evaluation module and the re sults of operation Topic Page 2 1 Overview 2 2 2 2 Applying an Input 2 3 2 3 Observing an Output 2 5 2 4 Typical Test Results 2 6 Chapter 2 ...

Page 14: ... VT VT is usually 2 V below the supply voltage of the driver circuit When the driver operates from a 3 3 V supply VT is set to approximately 1 3 V CML drivers are generally loaded with 50 Ω resistors to a termination voltage VTT VTT can either be equivalent to the supply voltage of the driver circuit equal to VCC or set to 2 5 V or 1 8 V irrelevant to the supply voltage If de sired the SN65CML100 ...

Page 15: ...lied to SMA connectors J4 and J5 while keeping R1 installed The EVM comes with a 100 Ω termination resistor R1 installed across the differential inputs This 100 Ω resistor represents an LVDS termination When using a general purpose signal generator with 50 Ω output impedance make sure that the signal levels are between 0 V to 4 V with respect to J3 A signal generator such as the Advantest D3186 ca...

Page 16: ...ential CML or LVPECL Inputs to EVM Select VT for LVPECL or Select VTT for CML Select VT for LVPECL or Select VTT for CML 50 Ω 50 Ω OUT OUT Signal Source EVM BOARD NOTES A Locate 50 Ω resistors as close to the EVM as possible B Remove R1 A B Y Z Finally as mentioned above the SN65LVDS100 SN65LVDS101 and SN65CML100 devices provide a VBB reference voltage output This output can be used with an extern...

Page 17: ...oscope inputs setting of the oscilloscope common mode offset voltage is required as the oscilloscope presents low common mode load impedance to the device Returning to Figure 2 2 power supply 1 is used to provide the required 3 3 V to the EVM Power supply 2 is used to offset the EVM ground relative to the DUT ground The EVM ground is connected to the oscilloscope ground through the returns on SMA ...

Page 18: ...pedance probe direct probing on the EVM is supported via installation of R2 R3 and R4 LVDS outputs can be observed by installing R4 a 100 Ω resistor LVPECL outputs can be observed by installing R2 and R3 49 9 Ω resistors and setting power supply 2 to 1 3 V CML outputs can be observed by setting power supply 2 to VTT and installing 49 9 Ω resistors at R2 and R3 for single termination or 24 9 Ω resi...

Page 19: ...Typical Test Results 2 7 Setup and Equipment Required Figure 2 5 Typical Output From SN65LVDS100 EVM ...

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Page 21: ...VM Construction This chapter lists the EVM components and examines the construction of the evaluation module Topic Page 3 1 Schematic 3 2 3 2 Bill of Materials 3 3 3 3 Board Stackup 3 4 3 4 Board Layer Patterns 3 5 Chapter 3 ...

Page 22: ...UT_MSOP8 DUT1 VCC01 VCC C11 010 µF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled R1 100 Ω J4 GND J5 GND 1 1 1 2 3 4 8 7 7 6 5 1 1 VCC VCC01 C1 10 µF C6 10 µF C2 68 µF C7 68 µF C3 1 µF C8 1 µF C4 0 1 µF C9 0 1 µF C5 0 001 µF 109 0 001 µF J1 1 J2 1 J3 1 MNTH1 MNTH2 MNTH3 MNTH4 ...

Page 23: ...K50V C11 C12 Capacitor SMT0603 50 V 10 0 010 µF 6 2 AVX 06033G102JATMA C5 C10 Capacitor SMT0603 25 V 5 0 001 µF 7 3 ITT Pomona 3267 J1 J2 J3 Connector banana jack Bannana jack 8 4 EF Johnson 142 0701 801 J4 J5 J6 J7 Connector SMA Jack end launch 0 062 9 1 Dale CRCW0603100F R1 Resistor SMT 0603 100 Ω 10 2 R2 R3 Resistor SMT 0603 49 9 Ω R2 R3 11 1 R4 Resistor SMT 0603 100 Ω R4 12 1 R5 Resistor SMT 0...

Page 24: ...d 2 LAMINATE MATERIAL NELCO N4000 13 DO NOT USE 13SI 3 COOPER WEIGHT 1 OZ START INTERNAL AND 1 2 OZ START EXTERNAL 4 FINISHED BOARD THICKNESS 062 10 5 MAXIMUM WARP AND TWIST TO BE 005 INCH PER INCH 6 MINIMUM COPPER WALL THICKNESS OF PLATED THRU HOLES TO BE 001 INCH 7 MINIMUM ANNULAR RING OF PLATED THRU HOLES TO BE 002 INCH 8 MINIMUM ALLOWABLE LINE REDUCTION TO BE 20 OR 002 WHICHEVER IS GREATER 9 0...

Page 25: ...Board Layer Patterns 3 5 EVM Construction 3 4 Board Layer Patterns Not to Scale Layer 1 Signal GND Fill Top Side Layer 2 GND Plane INT1 ...

Page 26: ...Board Layer Patterns 3 6 Layer 3 VCC Split Plane INT2 Layer 4 GND Plane Bottom Side ...

Page 27: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments SN65LVDS100EVM SN65LVDS101EVM SN65CML100EVM ...