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7.8.4
PLL2 Controller Input Clock Electrical Data/Timing
CLKIN2
2
3
4
4
5
1
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 7-39. Timing Requirements for CLKIN2
(1) (2) (3)
(see
Figure 7-30
)
-720
-850
A-1000/-1000
NO.
UNIT
-1200
MIN
MAX
1
t
c(CLKIN2)
Cycle time, CLKIN2
37.5
80
ns
2
t
w(CLKIN2H)
Pulse duration, CLKIN2 high
0.4C
ns
3
t
w(CLKIN2L)
Pulse duration, CLKIN2 low
0.4C
ns
4
t
t(CLKIN2)
Transition time, CLKIN2
1.2
ns
5
t
J(CLKIN2)
Period jitter (peak-to-peak), CLKIN2
100
ps
(1)
The reference points for the rise and fall transitions are measured at 3.3 V V
IL
MAX and V
IH
MIN.
(2)
C =
CLKIN2
cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.
(3)
If EMAC is enabled with RGMII or GMII, CLKIN2 cycle time must be 40 ns (25 MHz).
Figure 7-30. CLKIN2 Timing
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C64x+ Peripheral Information and Electrical Specifications
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