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Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
8
7
6
2
1
CLKX
FSX
DX
DR
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
(1) (2)
(see
Figure 7-56
)
-720
-850
A-1000/-1000
NO.
UNIT
-1200
MASTER
SLAVE
MIN
MAX
MIN
MAX
4
t
su(DRV-CKXH)
Setup time, DR valid before CLKX high
12
2 – 18P
ns
5
t
h(CKXH-DRV)
Hold time, DR valid after CLKX high
4
5 + 36P
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2)
For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7-67. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1
(1) (2)
(see
Figure 7-56
)
-720
-850
A-1000/-1000
NO.
PARAMETER
UNIT
-1200
MASTER
(3)
SLAVE
MIN
MAX
MIN
MAX
1
t
h(CKXH-FXL)
Hold time, FSX low after CLKX high
(4)
T – 2
T + 3
ns
2
t
d(FXL-CKXL)
Delay time, FSX low to CLKX low
(5)
H – 2
H + 3
ns
3
t
d(CKXL-DXV)
Delay time, CLKX low to DX valid
–2
4
18P + 2.8
30P + 17
ns
Disable time, DX high impedance following
6
t
dis(CKXH-DXHZ)
H – 2
H + 3
ns
last data bit from CLKX high
Disable time, DX high impedance following
7
t
dis(FXH-DXHZ)
6P + 3
18P + 17
ns
last data bit from FSX high
8
t
d(FXL-DXV)
Delay time, FSX low to DX valid
12P + 2
24P + 17
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2)
For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3)
S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = ( 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = ( 1)/2 * S if CLKGDV is odd
(4)
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5)
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
Figure 7-56. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
198
C64x+ Peripheral Information and Electrical Specifications
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