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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
C6000 DSP platforms.
SPRU970
TMS320C645x DSP DDR2 Memory Controller User's Guide.
This document describes the
DDR2 memory controller in the C645x digital-signal processors (DSPs).
SPRU966
TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide.
This document
describes the Enhanced DMA (EDMA3) Controller on the C645x device.
SPRU975
TMS320C645x DSP EMAC/MDIO Module User's Guide.
This document provides a
functional description of the Ethernet Media Access Controller (EMAC) and Physical layer
(PHY) device Management Data Input/Output (MDIO) module integrated with the devices of
the C645x family.
SPRU971
TMS320C645x DSP External Memory Interface (EMIF) User's Guide.
This document
describes the operation of the external memory interface (EMIF) in the digital signal
processors (DSPs) of the C645x DSP family.
SPRU724
TMS320C645x DSP General-Purpose Input/Output (GPIO) User's Guide.
This document
describes the general-purpose input/output (GPIO) peripheral in the digital signal processors
(DSPs) of the C645x DSP family. The GPIO peripheral provides dedicated general-purpose
pins that can be configured as either inputs or outputs. When configured as an input, you
can detect the state of the input by reading the state of an internal register. When configured
as an output, you can write to an internal register to control the state driven on the output
pin.
SPRU969
TMS320C645x DSP Host Port Interface (HPI) User's Guide.
This guide describes the host
port interface (HPI) on the C645x digital signal processors (DSPs). The HPI enables an
external host processor (host) to directly access DSP resources (including internal and
external memory) using a 16 bit (HPI16) or 32 bit (HPI32) interface.
SPRU974
TMS320C645x DSP Inter-Integrated Circuit (I2C) Module User's Guide.
This document
describes the inter-integrated circuit (I2C) module in the C645x Digital Signal Processor
(DSP). The I2C provides an interface between the C645x device and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and
connected by way of an I2C-bus. This document assumes the reader is familiar with the
I2C-bus specification.
SPRUE60
TMS320C645x DSP Peripheral Component Interconnect (PCI) User's Guide.
This
document describes the peripheral component interconnect (PCI) port in C645x devices. See
the PCI Specification revision 2.3 for details on the PCI interface.
SPRU976
TMS320C645x DSP Serial Rapid I/O User's Guide.
This document describes the Serial
Rapid IO (SRIO) on the C645x devices.
SPRUE56
TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL) Controller
User's Guide.
This document describes the operation of the software-programmable
phase-locked loop (PLL) controller in the C645x digital signal processors (DSPs). The PLL
controller offers flexibility and convenience by way of software-configurable multipliers and
dividers to modify the input signal internally. The resulting clock outputs are passed to the
C645x DSP core, peripherals, and other modules inside the C645x DSP.
SPRU968
TMS320C645x DSP 64 Bit Timer User's Guide.
This document provides an overview of the
64 bit timer in the C645x DSP. The timer can be configured as a general-purpose 64 bit
timer, dual general-purpose 32 bit timers, or a watchdog timer. When configured as a dual
32 bit timers, each half can operate in conjunction (chain mode) or independently (unchained
mode) of each other.
SPRU973
TMS320C645x DSP Turbo-Decoder Coprocessor (TCP) User's Guide.
Channel decoding
of high bit-rate data channels found in third generation (3G) cellular standards requires
decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP) in some of the digital
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Device Overview
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