SM320F2812-HT
www.ti.com
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
6.26 External Interface Ready-on-Write Timing With One External Wait State
Table 6-41. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
(1)
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
–
2
3
ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid
2
ns
t
d(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
2
ns
t
d(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
t
d(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
t
d(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
–
2
1
ns
t
en(XD)XWEL
Enable time, data bus driven from XWE low
0
ns
t
d(XWEL-XD)
Delay time, data valid after XWE active low
4
ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(2)
ns
t
h(XD)XWE
Hold time, write data valid after XWE inactive high
TW
–
2
(3)
ns
t
dis(XD)XRNW
Data bus disabled after XR/W inactive high
4
ns
(1)
Not production tested.
(2)
During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(3)
TW = trail period, write access (see
Table 6-25
)
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1) (2)
MIN
MAX
UNIT
t
su(XRDYsynchL)XCOHL
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
t
h(XRDYsynchL)
Hold time, XREADY (Synch) low
12
ns
t
e(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
3
ns
t
su(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
15
ns
t
h(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
(1)
Not production tested.
(2)
The first XREADY (Synch) sample occurs with respect to E in
Figure 6-33
:
E =(X XWRACTIVE) t
c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is
sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(X XWR n
–
1) t
c(XTIM)
–
t
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1) (2)
MIN
MAX
UNIT
t
su(XRDYasynchL)XCOHL
Setup time, XREADY (Asynch) low before XCLKOUT high/low
11
ns
t
h(XRDYasynchL)
Hold time, XREADY (Asynch) low
8
ns
t
e(XRDYasynchH)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
3
ns
t
su(XRDYasynchH)XCOHL
Setup time, XREADY (Asynch) high before XCLKOUT high/low
11
ns
t
h(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
(1)
Not production tested.
(2)
The first XREADY (Synch) sample occurs with respect to E in Figure 6-33:
E = (X XWRACTIVE
–
2) t
c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it is
sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (X XWRACTIVE
–
3 + n) t
c(XTIM)
–
t
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Electrical Specifications
125
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