Texas Instruments Stellaris RDK-IDM-SBC, User Manual

Stellaris® IDM Single-Board Computer

November 28, 2011

15

Power and Interface Terminal Block

Power, CAN, and I

2

C interfaces are provided through 3.5 mm pluggable terminal blocks. For 

convenience, the RDK includes the plugs. See the BOM for complete part numbers.

Figure 2-4.

Pluggable Terminal Blocks

I2C is a short-distance intra-device bus that can be used to add capabilities such as an ADC (for 
analog measurement) or digital inputs and outputs.

CAN is best suited for communication between devices. Refer to the CAN specification for 
complete details on data rates and bus length.

Clocking

The IDM-SBC board uses a 16.0-MHz (Y2) crystal to complete the LM3S9B92 microcontroller's 
main internal clock circuit. An internal PLL, configured in software, multiples this clock to higher 
frequencies for core and peripheral timing.

A 25.0 MHz (Y1) crystal provides an accurate timebase for the Ethernet PHY.

Reset

The RESETn signal into the LM3S39B92 microcontroller connects to the JTAG/SWD debug 
connector and to a simple R-C filter circuit to extend reset timing at power up.

The LCD Module has special Reset timing requirements requiring a dedicated control line from the 
microcontroller.

SDRAM

The LM3S9B92 features an External Peripheral Interface (EPI) module, a high-speed 8/16/32-bit 
parallel bus for connecting external peripherals or memory without glue logic. Supported modes 
include SDRAM, SRAM and Flash memories, as well as Host-bus and FIFO modes.

On the IDM-SBC, the SDRAM device interfaces directly to the EPI and adds 8MB of memory (4M 
x 16) which, once configured, becomes part of the LM3S9B92’s memory map at either 
0x6000.0000 or 0x8000.0000. 

The SDRAM interface multiplexes DQ00..14 and AD/BA0..14 without requiring external latches or 
buffers. Of the 32 EPI signals, only 24 are used in SDRAM mode, with the remaining signals used 
for non-EPI functions on the board.

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