25-MHz
LVCMOS
24-MHz
LVCMOS
to AM3359
6LWDUDŒ
25-MHz
LVCMOS
to DP83867IR PHY 2
CDCE913
to DP83867IR PHY 1
25-MHz
Crystal
25.001.250 Hz
24.998.750 Hz
Phase shift
4 ps
8 ps
500 Clocks 2 ns
YY
..
YY
..
System Overview
32
JAJU324B – March 2015 – Revised July 2017
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
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リファレンス・デザイン
2.3.1.4.2
Clock Distribution Circuits
Alternatively to the XTAL clocking as implemented on the TIDA-00204 reference design, a more advanced
clocking solution is possible. The following section describes how this could be implemented.
One reason for implementing a clock distribution circuit is to achieve high timing accuracy, which is
required for the real-time Ethernet protocols. A crystal can typically have around ±50 ppm in combined
tolerance and a stability specification at 25°C, which means that a 25-MHz crystal with 50 ppm can
potentially run at 25 MHz ±1250 Hz.
When running several crystals, the phase shift between the two crystals can potentially be maximum
negative and maximum positive, which
shows.
図
図
17. Crystal Phase Shift Diagram
This distribution means that, depending on how many clocks are seen on a signal package, the phase
shift of the two clocks accumulates. Avoid this accumulation by adding a clocking distribution network.
After this action, only the one clock cycle jitter requires consideration and the phase shift is no longer a
concern.
The solution to this problem is to replace XTALs of the PHY and Sitara chips with a CDCE913
programmable 1-PLL VCXO clock synthesizer, with three outputs. If more than three clocks are required,
the CDCE9xx device family is available with various output and maximum output clock frequency.
This solution yields several advantages in general:
•
High accurate clocking with minimum frequency and phase shift
•
Smaller component area used for clocking
•
Potentially lower cost
•
Possibility to extend easily
shows how a CDCE913 could be connected and used to provide three reference LVCMOS clocks.
図
図
18. CDCE913 Clock Distribution Circuit Example
