i.MX6 ULL
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_SDWE_B
DRAM_ODT0
DRAM_CS1_B
DRAM_ODT1
DRAM_SDCKE1
DRAM_ZQPAD
MT41K256M16TW-107:P
DQ[15:0]
LDQS/LDQS#
UDQS/UDQS#
LDM/UDM
CS#
RAS#
CAS#
WE#
ODT
ZQ
NC1
NC2
NC3
NVCC_DRAM_1V35
DRAM_VREF
NVCC_DRAM
DRAM_VREF
NVCC_DRAM_2P5
DRAM_DATA[15:00]
DRAM_SDQS0_P/N
DRAM_SDQS1_P/N
DRAM_DQM[1:0]
VDD_HIGH_CAP
240 E
240 E
10 K
DRAM_ADDR[15:00]
DRAM_ADDR[15]
DRAM_SDBA[2:0]
DRAM_SDCLK0_P/N
DRAM_SDCKE0
DRAM_RESET_B
A[14:0]
NC4
BA[2:0]
CK/CK#
CKE
RESET#
VDD
VDDQ
NVCC_DRAM_1V35
VREFDQ VREFCA
DRAM_VREF
NVCC_DRAM_1V35
1.5 K
1.5 K
DRAM_VREF
VSS/VSSQ
VSS
DRAM_SDCLK0_P
DRAM_SDCLK0_N
470 E
DRAM_SDQS0_P
2.2 pF
DRAM_SDQS0_N
DRAM_SDQS1_P
DRAM_SDQS1_N
2.2 pF
System Overview
5
TIDUEW7 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Integrated Power Supply Reference Design for NXP i.MX 6ULL
2.2.2
i.MX 6ULL Memory Interfaces
This project makes use of i.MX 6ULL processor’s four different external memory interfaces using 4-Gb
DDR3L (512 MB), 256-Mb QSPI NOR-Flash (32 MB), 8-GB eMMC 5.0, and SD v3.0.
2.2.2.1
DDR3L
i.MX 6ULL has a dedicated DDR memory controller which supports 16-bit LP-DDR2-800, DDR3-800, and
DDR3L-800, all of which can operate up to 800 MT/s data rate. This design is provided with single 4-Gb
x16 (512 MB) DDR3L memory. Micron’s MT41K256M16TW-107:P is a 4-Gb DDR3L SDRAM used in this
design. The memory interface comprises of single channel of 16-bit data signals, along with command and
address signals. The DDR interface is shown in
.
DESCRIPTION
MFG.
PART NUMBER
IC, DDR3L SDRAM, 512MB, x16bit, 1866 MT/s, FBGA-
96
Micron
MT41K256M16TW-107:P
Figure 2. DDR3L Interface