MRAM Memory
(2 kB)
0x8000
SID Filters
XID Filters
Rx FIFO 0
Rx FIFO 1
0x8008
0x8010
0x80F0
0x8258
Tx Event FIFO
0x8270
Tx Buffers
0x87FF
Firmware
15
SLLU216 – July 2019
Copyright © 2019, Texas Instruments Incorporated
SPI to CAN FD SBC + LIN Transceiver BoosterPack User's Guide
Each CAN bit is over-sampled by the controller and the interval between these samples is called a time
quanta (tq). The four segments of the bit are defined in units of tq and these values must be programmed
into the controller. The crystal or clock input frequency determines the minimum tq (1/frequency). The
BoosterPack uses a 40-MHz crystal as its clock source and can have a prescaler applied to adjust the
sample clock frequency to achieve the desired tq for the data rate. For example, if the 1:4 prescaler was
applied to the 40-MHz input clock, the sample clock would be 10 Mhz. If we wanted the data rate to be 1-
Mbps, this would yield 10 tq per bit. The four segments of the bit could then be defined with 1 tq for the
sync_seg, 3 tq for the prop_seg, 4 tq for prop_seg1, and 2 tq for prop_seg2. This would place the sample
point at 80% of the bit period allowing enough time for the signal to propagate through the bus.
There must be an integer multiple of tq per bit period and therefore these settings must be adjusted for the
desired data rate that is used on the bus as well as any accommodations needed for the propagation
delay of the bus used. CAN applications only use one data rate for the arbitration and data portions of a
CAN packet. CAN FD applications need to calculate and program the settings for both the arbitration data
rate and the faster data payload data rate.
NOTE:
No segment can be equal to 0 tq, yet this is a valid value to be input to the TCAN4550-Q1
registers for the CAN bit timing. Therefore the TCAN4550-Q1 interprets the values input to
the registers as 1 greater than the input value. For example, if the raw value for the timing
parameter is 4, the register value should be set with a value of 3.
3.1.2
Message RAM Setup
Figure 8. Visual representation of MRAM allocation
