Program Description
3-15
Operation
3.5.2.3
Audio PLL Section
On the audio codec part of the AIC26, there is an on-chip phase-lock-loop
(PLL). The PLL can be enabled or disabled, based on the given master clock
(MCLK) to the AIC26 and the required reference frequency (FSref) for the
codec. For more details on the PLL, refer to the AIC26 data sheet.
With the EVM board, the MCLK is at 11.2896 MHz, and the codec sample rate
is also fixed at 44.1 kHz. So no PLL is necessary.
With the AIC26EVM, changing the PLL setting may cause audio
distortions.
3.5.2.4
Reinitialization and Reset
There are two buttons on this screen that allow the user to reset and reinitialize
the AIC26 by clicking these buttons.
By clicking the button SW Reset , a software reset is issued. By clicking the
button Init
AIC26 , the control registers (for ADC and audio) revert back to
the startup (firmware) default settings.
To bring the AIC26 EVM back to its powerup status, you can clicking
SW Reset and followed by
Init AIC26
.
Summary of Contents for TLV320AIC26EVM
Page 12: ...1 4 THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 15: ...Quick Start 2 3 Getting Started Figure 2 1 Default Software Screen ...
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Page 26: ...Program Description 3 10 Figure 3 1 Data Acquisition Screen With ADC Registers Reading ...
Page 28: ...Program Description 3 12 Figure 3 3 Data Acquisition Screen With Boost Filter Parameters ...
Page 37: ...3 21 Operation THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 39: ...Component Locations 4 2 4 1 Component Locations ...