Key Features of the TMS320C2xx
1-7
Introduction
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Instruction set:
J
Single-instruction repeat operation
J
Single-cycle multiply/accumulate instructions
J
Memory block move instructions for better program/data
management
J
Indexed-addressing capability
J
Bit-reversed indexed-addressing capability for radix-2 FFTs
-
On-chip peripherals:
J
Software-programmable timer
J
Software-programmable wait-state generator for program, data, and
I/O memory spaces
J
Oscillator and phase-locked loop (PLL) to implement clock options:
×
1,
×
2,
×
4, and
÷
2 (only
×
2 and
÷
2 available on ’C209)
J
CLK register for turning the CLKOUT1 pin on and off (not available on
’C209)
J
Synchronous serial port (not available on ’C209)
J
Asynchronous serial port (not available on ’C209)
-
On-chip scanning-logic circuitry (IEEE Standard 1149.1) for emulation
and testing purposes
-
Power:
J
5- or 3.3-V static CMOS technology
J
Power-down mode to reduce power consumption
-
Packages:
J
100-pin TQFP (thin quad flat pack)
J
80-pin TQFP for the ’C209
