2-1
Architectural Overview
Architectural Overview
This chapter provides an overview of the architectural structure and compo-
nents of the ’C2xx. The ’C2xx DSPs use an advanced, modified Harvard archi-
tecture that maximizes processing power by maintaining separate bus struc-
tures for program memory and data memory. The three main components of
the ’C2xx are the central processing unit (CPU), memory, and on-chip periph-
erals.
Figure 2–1 shows an overall block diagram of the ’C2xx.
Note:
All ’C2xx devices use the same central processing unit (CPU), bus structure,
and instruction set, but the ’C209 has some notable differences. For exam-
ple, although certain peripheral control registers have the same names on
all ’C2xx devices, these registers are located at different I/O addresses on
the ’C209. See Chapter 11 for a detailed description of the differences on the
’C209.
Topic
Page
2.1
’C2xx Bus Structure
2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Central Processing Unit
2-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Memory and I/O Spaces
2-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Program Control
2-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
On-Chip Peripherals
2-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Scanning-Logic Circuitry
2-13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2
