Transmitter Operation
9-22
9.5.4
Continuous Mode Transmission with External Frame Sync (FSM=0, TXM=0)
Use continuous mode transmission with external frame sync to transfer long
packets at maximum packet frequency while using an external frame sync
generator. Place the transmitter in continuous mode with external frame sync
by setting the FSM bit to 0 and the TXM bit to 0.
In continuous mode, frame sync pulses are not necessary after the initial pulse
for consecutive packet transfers. A frame sync is generated only for the first
transmission. As long as the FIFO buffer has new values to transmit, the mode
continues. Transmission halts when the buffer empties. If SDTR is written to
after the halt, the device starts a new continuous mode transmission.
This mode of operation offers several features:
-
Only one frame sync is necessary for the transmission of consecutive
packets.
-
If the FIFO buffer is not empty, the mode continues. If the FIFO buffer is
empty, the process ends.
Generally, the transmit clock and the receive clock have the same source. This
allows each bit to be transmitted from another device on a rising edge of the
clock signal and received by the ’C2xx on the next falling edge of the clock sig-
nal.
Continuous mode transmission with external frame sync requires the following
order of events (see Figure 9–7):
1) A frame sync pulse initiates the transmission. The pulse is sampled on the
falling edge of CLKX. After the falling edge of CLKX, the contents of the
current word in the transmit FIFO buffer are transferred to the XSR. If the
FIFO buffer becomes empty during this operation, then it generates a
XINT to request more data.
2) On the next rising edge of CLKX after FSX goes high, DX is driven with
the first bit (MSB) of the word to be transmitted.
3) The frame sync goes low (and remains low during word transmission).
4) Once FSX goes low, the rest of the bits are shifted out.
5) Once the entire word in the XSR is shifted out, the next word is loaded in
and the first bit of the word is placed on the DX pin. Then, the process re-
peats beginning with step four. If a new word is not in the transmit FIFO
buffer, then the process ends.
If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the
new word will be lost; the FIFO buffer will not accept any more than four words.
