Controlling and Resetting the Port
10-18
TXRXINT leads the CPU to interrupt vector location 000Ch in program
memory. The branch at that location should lead to an interrupt service routine
that identifies the cause of the interrupt and then acts accordingly. TXRXINT
has a priority level of 9 (1 being highest).
TXRXINT is a maskable interrupt and is controlled by the interrupt mask regis-
ter (IMR) and interrupt flag register (IFR).
Note:
To avoid a double interrupt from the ASP, clear the IFR bit (TXRXINT) in the
corresponding interrupt service routine, just before returning from the rou-
tine.
