3-2
Figure 3–1. Block Diagram of the Input Scaling, Central Arithmetic Logic, and
Multiplication Sections of the CPU
32
Input shifter (32 bits)
16
32
Output shifter (32 bits)
32
C
Accumulator
CALU
32
32
MUX
32
16
MUX
MUX
16
16
PREG
Multiplier
16
×
16
16
Data write bus (DWEB)
Data read bus (DRDB)
TREG
16
16
Program read bus (PRDB)
16
16
1
1
Product shifter (32 bits)
16
Central arithmetic logic
section
Multiplication
section
31
0
16 15
32
1
Input scaling
section
1
Central Processing Unit
